Message ID | 20220409120819.3124209-1-gch981213@gmail.com |
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Sat, 09 Apr 2022 05:08:51 -0700 (PDT) From: Chuanhong Guo <gch981213@gmail.com> To: linux-spi@vger.kernel.org Cc: Chuanhong Guo <gch981213@gmail.com>, Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Miquel Raynal <miquel.raynal@bootlin.com>, Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Roger Quadros <rogerq@kernel.org>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>, Cai Huoqing <cai.huoqing@linux.dev>, Florian Fainelli <f.fainelli@gmail.com>, Colin Ian King <colin.king@intel.com>, Wolfram Sang <wsa+renesas@sang-engineering.com>, Paul Cercueil <paul@crapouillou.net>, Pratyush Yadav <p.yadav@ti.com>, Yu Kuai <yukuai3@huawei.com>, devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-kernel@vger.kernel.org (open list), linux-mtd@lists.infradead.org (open list:NAND FLASH SUBSYSTEM) Subject: [PATCH v5 0/5] spi: add support for Mediatek SPI-NAND controller Date: Sat, 9 Apr 2022 20:08:14 +0800 Message-Id: <20220409120819.3124209-1-gch981213@gmail.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: <devicetree.vger.kernel.org> X-Mailing-List: devicetree@vger.kernel.org |
Series |
spi: add support for Mediatek SPI-NAND controller
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On Sat, Apr 9, 2022 at 8:08 PM Chuanhong Guo <gch981213@gmail.com> wrote: > > Mediatek has an extended version of their NAND Flash Interface which > has a SPI-NAND mode. In this mode, the controller can perform 1-bit > spi-mem ops for up-to 0xa0 bytes and typical SPI-NAND single, dual > and quad IO page cache ops with 2-byte address. Additionally, the > page cache ops can be performed with ECC and auto data formatting > using the ECC engine of the controller. There are two missing register configurations in this series. It wasn't affecting me back then because the bootloader set them for me. I'll send a v6 soon.