| Message ID | 20220208183511.2925304-1-jjhiblot@traphandler.com |
|---|---|
| Headers | show |
| Series | ARM: r9a06g032: add support for the watchdogs | expand |
Hi Jean-Jacques, On Tue, Feb 8, 2022 at 7:35 PM Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > This SOC includes 2 watchdog controllers (one per A7 core). > > Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Thanks for your patch! > --- a/arch/arm/boot/dts/r9a06g032.dtsi > +++ b/arch/arm/boot/dts/r9a06g032.dtsi > @@ -66,6 +66,22 @@ soc { > interrupt-parent = <&gic>; > ranges; > > + wdt0: watchdog@40008000 { > + compatible = "renesas,r9a06g032-wdt"; compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; > + reg = <0x40008000 0x1000>; > + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; > + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; > + status = "disabled"; > + }; > + > + wdt1: watchdog@40009000 { > + compatible = "renesas,r9a06g032-wdt"; compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; > + reg = <0x40009000 0x1000>; > + interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; > + clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; > + status = "disabled"; > + }; > + > sysctrl: system-controller@4000c000 { > compatible = "renesas,r9a06g032-sysctrl"; > reg = <0x4000c000 0x1000>; > -- > 2.25.1 >
On Tue, Feb 8, 2022 at 7:35 PM Jean-Jacques Hiblot <jjhiblot@traphandler.com> wrote: > 60s is a sensible default value. > > Signed-off-by: Jean-Jacques Hiblot <jjhiblot@traphandler.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi all, This series adds support for the watchdog timers of the RZ/N1. The watchdog driver (rzn1-wdt.c) is derived from the driver available at https://github.com/renesas-rz/rzn1_linux.git with a few modifications In order to be able to reset the board when a watchdog timer expires, the RSTEN register must be configured. it is the responsability of the bootloader to set those bits (or not, depending on the chosen policy). If the watchdog reset source is not enabled, an interrupt is triggered when the watchdog expires. Currently this interrupt doesn't much apart from printing a message. Changes v1 -> v2: * Modified the clock driver to not enable the watchdog reset sources. On other renesas platforms, those bits are by the bootloader. The watchdog reset sources are still disabled when the platform is halted to prevent a watchdog reset. * Added a SOC-specific compatible "renesas,r9a06g032-wdt" * reordered the dts/i entries * default timeout is 60 seconds * reworked the probe function of the wdt driver to better error cases * removed the set_timeout() and use a fixed period computed in probe(). This removes the confusion and makes it clear that the period defined by the user space in indeed handled by the watchdog core Jean-Jacques Hiblot (5): dt-bindings: clock: r9a06g032: Add the definition of the the watchdog clock dt-bindings: watchdog: renesas,wdt: Add support for RZ/N1 ARM: dts: r9a06g032: Add the watchdog nodes ARM: dts: r9a06g032-rzn1d400-db: Enable watchdog0 with a 60s timeout clk: renesas: r9a06g032: Disable the watchdog reset sources when halting Phil Edworthy (1): watchdog: Add Renesas RZ/N1 Watchdog driver .../bindings/watchdog/renesas,wdt.yaml | 6 + arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 5 + arch/arm/boot/dts/r9a06g032.dtsi | 16 ++ drivers/clk/renesas/r9a06g032-clocks.c | 30 +++ drivers/watchdog/Kconfig | 8 + drivers/watchdog/Makefile | 1 + drivers/watchdog/rzn1_wdt.c | 208 ++++++++++++++++++ include/dt-bindings/clock/r9a06g032-sysctrl.h | 1 + 8 files changed, 275 insertions(+) create mode 100644 drivers/watchdog/rzn1_wdt.c