| Message ID | 20201008003746.25659-1-nicoleotsuka@gmail.com |
|---|---|
| Headers | show |
| Series | memory: tegra: Fix client list and add swgroups | expand |
On Thu, 8 Oct 2020 at 02:44, Nicolin Chen <nicoleotsuka@gmail.com> wrote: > > This series has two fixes of tegra210_mc_clients, and three > changes to add missing swgroups, according to Tegra X1 TRM. > > Nicolin Chen (5): > memory: tegra: Correct la.reg address of seswr > memory: tegra: Correct tegra210_mc_clients def values > memory: tegra: Sort tegra210_swgroups by reg address > dt-bindings: memory: tegra: Add missing swgroups > memory: tegra: Complete tegra210_swgroups Hi, It's too late in the cycle for another pull request so this will wait for merge window to finish. Best regards, Krzysztof
On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote: > This is a cleanup change to prepare for new swgroups. What type of cleanup? Any functional change? > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c > index e8a7d266802c..b400802c9f14 100644 > --- a/drivers/memory/tegra/tegra210.c > +++ b/drivers/memory/tegra/tegra210.c > @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { > }; > > static const struct tegra_smmu_swgroup tegra210_swgroups[] = { > - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, > - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, > { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 }, > { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, > - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, > + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, > + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, > { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, > + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, > + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, > { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, > { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, > - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, > + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, > + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, > { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 }, > { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, > - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, > - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, > { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, I must say I cannot find the order. By name - not. By swgroup name - not. By register - not. What is the order then? Best regards, Krzysztof > - { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, > + { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, > { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 }, > { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 }, > { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c }, > { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 }, > - { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, > - { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, > + { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, > + { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, > { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 }, > { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 }, > - { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, > { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc }, > + { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, > { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc }, > { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 }, > { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 }, > -- > 2.17.1 >
Hi Krzysztof, On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote: > On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote: > > This is a cleanup change to prepare for new swgroups. > > What type of cleanup? Any functional change? It's to sort the swgroup list by reg address as I mentioned in the subject. Perhaps I should have put in commit message also. > > > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > > --- > > drivers/memory/tegra/tegra210.c | 20 ++++++++++---------- > > 1 file changed, 10 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c > > index e8a7d266802c..b400802c9f14 100644 > > --- a/drivers/memory/tegra/tegra210.c > > +++ b/drivers/memory/tegra/tegra210.c > > @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { > > }; > > > > static const struct tegra_smmu_swgroup tegra210_swgroups[] = { > > - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, > > - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, > > { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 }, > > { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, > > - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, > > + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, > > + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, > > { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, > > + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, > > + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, > > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, > > { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, > > { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, > > - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, > > + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, > > + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, > > { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 }, > > { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, > > - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, > > - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, > > { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, > > I must say I cannot find the order. By name - not. By swgroup name - > not. By register - not. > > What is the order then? It's by "reg" as I mentioned in the commit subject. Probably it's not that obvious by looking at the change itself :-/ Its following change of adding new swgroups would be easier to insert by following the same order of "reg" addresses. Thanks
Hi Krzysztof, On Thu, Oct 08, 2020 at 12:29:06PM +0200, Krzysztof Kozlowski wrote: > On Thu, 8 Oct 2020 at 02:44, Nicolin Chen <nicoleotsuka@gmail.com> wrote: > > > > This series has two fixes of tegra210_mc_clients, and three > > changes to add missing swgroups, according to Tegra X1 TRM. > > > > Nicolin Chen (5): > > memory: tegra: Correct la.reg address of seswr > > memory: tegra: Correct tegra210_mc_clients def values > > memory: tegra: Sort tegra210_swgroups by reg address > > dt-bindings: memory: tegra: Add missing swgroups > > memory: tegra: Complete tegra210_swgroups > > Hi, > > It's too late in the cycle for another pull request so this will wait > for merge window to finish. I see. Thanks for telling me this!
On Wed, Oct 07, 2020 at 05:37:42PM -0700, Nicolin Chen wrote: > According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field > [23:16] of register at address 0x3e0 with a reset value of 0x80 > at register 0x3e0, while bit-1 of register 0xb98 is for enable > bit of seswr. So this patch fixes it. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c > index 7fb8b5438bf4..088814279616 100644 > --- a/drivers/memory/tegra/tegra210.c > +++ b/drivers/memory/tegra/tegra210.c > @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { > .bit = 1, > }, > .la = { > - .reg = 0xb98, > + .reg = 0x3e0, > .shift = 16, > .mask = 0xff, > .def = 0x80, Heh, indeed. Look like I copied the reg offset from the .smmu.reg by mistake. Acked-by: Thierry Reding <treding@nvidia.com>
On Wed, Oct 07, 2020 at 05:37:43PM -0700, Nicolin Chen wrote: > Some def values are mismatched with Tegra X1 TRM, probably because > being copied from tegra124.c file. So this patch fixes them. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) Looks good: Acked-by: Thierry Reding <treding@nvidia.com>
On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote: > This is a cleanup change to prepare for new swgroups. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) Acked-by: Thierry Reding <treding@nvidia.com>
On Thu, Oct 08, 2020 at 01:26:16PM -0700, Nicolin Chen wrote: > Hi Krzysztof, > > On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote: > > On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote: > > > This is a cleanup change to prepare for new swgroups. > > > > What type of cleanup? Any functional change? > > It's to sort the swgroup list by reg address as I mentioned in > the subject. Perhaps I should have put in commit message also. Indeed it is sorted by regs, I missed some numbers... looks good. I can adjust the commit msg so no need for resend. Best regards, Krzysztof
On Mon, Oct 12, 2020 at 06:43:40PM +0200, Krzysztof Kozlowski wrote: > On Thu, Oct 08, 2020 at 01:26:16PM -0700, Nicolin Chen wrote: > > Hi Krzysztof, > > > > On Thu, Oct 08, 2020 at 12:32:58PM +0200, Krzysztof Kozlowski wrote: > > > On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote: > > > > This is a cleanup change to prepare for new swgroups. > > > > > > What type of cleanup? Any functional change? > > > > It's to sort the swgroup list by reg address as I mentioned in > > the subject. Perhaps I should have put in commit message also. > > Indeed it is sorted by regs, I missed some numbers... looks good. I can > adjust the commit msg so no need for resend. Thank you!
On Wed, Oct 07, 2020 at 05:37:42PM -0700, Nicolin Chen wrote: > According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field > [23:16] of register at address 0x3e0 with a reset value of 0x80 > at register 0x3e0, while bit-1 of register 0xb98 is for enable > bit of seswr. > So this patch fixes it. Either use the imperative form ("Fix foo bar register address") or just skip the last sentence as it is quite obvious. https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L151 Thanks, applied. Best regards, Krzysztof
On Wed, Oct 07, 2020 at 05:37:43PM -0700, Nicolin Chen wrote: > Some def values are mismatched with Tegra X1 TRM, probably because > being copied from tegra124.c file. So this patch fixes them. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) Thanks, applied. Best regards, Krzysztof
On Wed, Oct 07, 2020 at 05:37:44PM -0700, Nicolin Chen wrote: > This is a cleanup change to prepare for new swgroups. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) Thanks, applied with adjusted commit msg (use imperative mode, so "Cleanup list of ..."). Best regards, Krzysztof
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote: > According to Tegra X1 TRM, there are missing swgroups in the > tegra210_swgroups list. So this patch adds them to the list. > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps > TEGRA_SWGROUP_GPU (in list) as it is. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c > index b400802c9f14..b3bbc5a05ba1 100644 > --- a/drivers/memory/tegra/tegra210.c > +++ b/drivers/memory/tegra/tegra210.c > @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = { > { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, > { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, > + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 }, > + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c }, Oddly enough I can see these in the TRM, but they are not in the internal reference manuals that are supposed to be the canonical reference for the TRM. Perhaps the TRM is out of date? Thierry
On Tue, Oct 27, 2020 at 02:01:11PM +0100, Thierry Reding wrote: > On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote: > > According to Tegra X1 TRM, there are missing swgroups in the > > tegra210_swgroups list. So this patch adds them to the list. > > > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually > > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) > > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So > > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps > > TEGRA_SWGROUP_GPU (in list) as it is. > > > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > > --- > > drivers/memory/tegra/tegra210.c | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c > > index b400802c9f14..b3bbc5a05ba1 100644 > > --- a/drivers/memory/tegra/tegra210.c > > +++ b/drivers/memory/tegra/tegra210.c > > @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = { > > { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, > > { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, > > { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, > > + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 }, > > + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c }, > > Oddly enough I can see these in the TRM, but they are not in the > internal reference manuals that are supposed to be the canonical > reference for the TRM. Perhaps the TRM is out of date? Hmm..I actually have been using the TRM from official site all the time. These two aren't being used downstream either; I put them in the patch merely because they exist in the TRM. So we may drop them if you feel that's better.
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote: > According to Tegra X1 TRM, there are missing swgroups in the > tegra210_swgroups list. So this patch adds them to the list. > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps > TEGRA_SWGROUP_GPU (in list) as it is. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) Acked-by: Thierry Reding <treding@nvidia.com>
On Wed, Oct 07, 2020 at 05:37:46PM -0700, Nicolin Chen wrote: > According to Tegra X1 TRM, there are missing swgroups in the > tegra210_swgroups list. So this patch adds them to the list. > > Note that the TEGRA_SWGROUP_GPU (in list) should be actually > TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) > is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So > this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps > TEGRA_SWGROUP_GPU (in list) as it is. > > Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> > --- > drivers/memory/tegra/tegra210.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) Thanks, applied. Best regards, Krzysztof