From patchwork Wed Apr 17 05:27:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Bai X-Patchwork-Id: 1086785 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="WRLiwbeB"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44kW2v0s7Gz9s8m for ; Wed, 17 Apr 2019 15:27:35 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730082AbfDQF1e (ORCPT ); Wed, 17 Apr 2019 01:27:34 -0400 Received: from mail-eopbgr10055.outbound.protection.outlook.com ([40.107.1.55]:20614 "EHLO EUR02-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725811AbfDQF1d (ORCPT ); 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DIR:OUT; SFP:1101; SCL:1; SRVR:VI1PR0402MB3552; H:VI1PR0402MB3519.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: dLWJmCq9V1WXPPAePGC4ATVqZAiRHmr/v1gQVWpeGA90+tCnABCfoqlR/au4qt1U8/VdnE1IvReqrIimJf/3x/xaLgzJvtD1dYOfjhkDC+wVrEz+FMRkWtjtPCocil3hcuWiyP721gq51FSihGL5aSRE2H24XVDq6OPNhJfv/PHNhKuMZhfnki8oifCPH3rp9xaXkVS/W9fPjZZkIgH8BsPwm4lfsWT5zIWHQoGf4fzzNLeuVaaR8+Nw2J0qNMTnkA3XBVwJMdMj+tVhty2Bh4jOav815hjRILRdGsp1SWsjvgYysMItV1OnX752m1qn4gDQMd1B1uDL3msG/eFHBnazvWaXstSM9BGMo7WxASRvTlP1OmypSrRIpXE4RUpRTAifdW0DslJXUyzKY0F08zmlYZiCxdJ9cIVJTCPqqnc= MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2afd8fc1-b580-4760-1f70-08d6c2f55f62 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Apr 2019 05:27:24.7639 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3552 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The i.MX8M family is a set of NXP product focus on delivering the latest and greatest video and audio experience combining state-of-the-art media-specific features with high-performance processing while optimized for lowest power consumption. i.MX8MQ, i.MX8MM, i.MX8MN, even the furture i.MX8MP are all belong to this family. The GPC module is used to manage the PU power domains' power on/off. For the whole i.MX8M family, different SoC has differnt power domain design. the power up sequence has significant difference. all the power sequence must be guaranteed by SW. Some domains' power up sequence need to access the SRC module or sub-system specific GPR. the SRC register & SS's register are not in in the GPC's memory range. it makes us hard to use the GPCv2 driver to cover all the different power up requirement. Each time, a new SoC is added, we must modify the GPCv2 driver to make it resuable for it. a lot of code need to be added in GPCv2 to support it. we need to access the SRC & SS' GPR, then the GPCv2 driver can NOT be self-contained. Accessing the non-driver specific module's register is a bad practice. Although, the GPC module provided the similar function for PU power domain, but it is not 100% compatible with GPCv2. The most important thing is that the GPC & SRC module is a security critical resource that security permission must be considered when building the security system. The GPC module is not only used by PU power domain power on/off. It is also used by the TF-A PSCI code to do the CPU core power management. the SRC module control the CPU CORE reset and the CPU reset vector address. if we give the non-secure world write permission to SRC. System can be easily induced to malicious code. This patchset add a more generic power domain driver that give us the possibility to use one driver to cover the whole i.MX8M family power domain in kernel side. kernel side doesn't need to handle the power domain difference anymore, all the sequence can be abstracted & handled in TF-A side. Most important, We don't need to care if the GPC & SRC is security protected. Jacky Bai (3): dt-bindings: power: Add power domain binding for i.mx8m family soc: imx: Add power domain driver support for i.mx8m family arm64: dts: freescale: Add power domain nodes for i.mx8mm .../bindings/power/fsl,imx8m-genpd.txt | 46 ++++ arch/arm64/boot/dts/freescale/imx8mm.dtsi | 103 ++++++++ drivers/soc/imx/Kconfig | 6 + drivers/soc/imx/Makefile | 1 + drivers/soc/imx/imx8m_pm_domains.c | 224 ++++++++++++++++++ include/soc/imx/imx_sip.h | 12 + 6 files changed, 392 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt create mode 100644 drivers/soc/imx/imx8m_pm_domains.c create mode 100644 include/soc/imx/imx_sip.h