| Message ID | 20190312152256.35574-1-icenowy@aosc.io |
|---|---|
| Headers | show |
| Series | Support for Allwinner V3/S3L and Sochip S3 | expand |
On Tue, Mar 12, 2019 at 11:22:46PM +0800, Icenowy Zheng wrote: > Introduce the GPIO pins that is only available on V3 (not on V3s) to the > V3 pinctrl driver. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c | 291 +++++++++++++++++++++-- > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + > 2 files changed, 275 insertions(+), 18 deletions(-) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > index 6704ce8e5e3d..54c210871a95 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > @@ -1,5 +1,5 @@ > /* > - * Allwinner V3s SoCs pinctrl driver. > + * Allwinner V3/V3s SoCs pinctrl driver. > * > * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> > * > @@ -23,7 +23,7 @@ > > #include "pinctrl-sunxi.h" > > -static const struct sunxi_desc_pin sun8i_v3s_pins[] = { > +static const struct sunxi_desc_pin sun8i_v3_v3s_pins[] = { I'm not sure all that remaining is worth it to be honest. It adds a lot of noise for no particular reason (and the same goes for renaming the file itself). Maxime
于 2019年3月12日 GMT+08:00 下午11:36:54, Maxime Ripard <maxime.ripard@bootlin.com> 写到: >On Tue, Mar 12, 2019 at 11:22:46PM +0800, Icenowy Zheng wrote: >> Introduce the GPIO pins that is only available on V3 (not on V3s) to >the >> V3 pinctrl driver. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c | 291 >+++++++++++++++++++++-- >> drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + >> 2 files changed, 275 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c >b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c >> index 6704ce8e5e3d..54c210871a95 100644 >> --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c >> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c >> @@ -1,5 +1,5 @@ >> /* >> - * Allwinner V3s SoCs pinctrl driver. >> + * Allwinner V3/V3s SoCs pinctrl driver. >> * >> * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> >> * >> @@ -23,7 +23,7 @@ >> >> #include "pinctrl-sunxi.h" >> >> -static const struct sunxi_desc_pin sun8i_v3s_pins[] = { >> +static const struct sunxi_desc_pin sun8i_v3_v3s_pins[] = { > >I'm not sure all that remaining is worth it to be honest. It adds a >lot of noise for no particular reason (and the same goes for renaming >the file itself) Maybe keeping names is okay "for historial reasons". In fact I want to keep them. > >Maxime
Hi Icenowy, Le mardi 12 mars 2019 à 23:22 +0800, Icenowy Zheng a écrit : > Introduce the GPIO pins that is only available on V3 (not on V3s) to the > V3 pinctrl driver. Thanks for working on this, I was actually close to submitting similar patches for V3 support! I just reviewed the definitions and found a mistakes about the LVDS function (that should be 0x3 instead of 0x2). Otherwise, things look good and match what I had came up with. Cheers, Paul > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c | 291 +++++++++++++++++++++-- > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + > 2 files changed, 275 insertions(+), 18 deletions(-) > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > index 6704ce8e5e3d..54c210871a95 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > @@ -1,5 +1,5 @@ > /* > - * Allwinner V3s SoCs pinctrl driver. > + * Allwinner V3/V3s SoCs pinctrl driver. > * > * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> > * > @@ -23,7 +23,7 @@ > > #include "pinctrl-sunxi.h" > > -static const struct sunxi_desc_pin sun8i_v3s_pins[] = { > +static const struct sunxi_desc_pin sun8i_v3_v3s_pins[] = { > /* Hole */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), > SUNXI_FUNCTION(0x0, "gpio_in"), > @@ -77,6 +77,30 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { > SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ > SUNXI_FUNCTION(0x3, "uart0"), /* RX */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "jtag"), /* MS */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "jtag"), /* CK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "jtag"), /* DO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "jtag"), /* DI */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */ > /* Hole */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), > SUNXI_FUNCTION(0x0, "gpio_in"), > @@ -98,6 +122,180 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */ > SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */ > + /* Hole */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ > + SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ > + SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D4 */ > + SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ > + SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ > + SUNXI_FUNCTION(0x4, "emac")), /* RXCK */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ > + SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ > + SUNXI_FUNCTION(0x4, "emac")), /* RXERR */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ > + SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ > + SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ > + SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ > + SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ > + SUNXI_FUNCTION(0x4, "emac")), /* CRS */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ > + SUNXI_FUNCTION(0x2, "lvds"), /* VP0 */ LVDS should be function 0x3. > + SUNXI_FUNCTION(0x4, "emac")), /* TXCK */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ > + SUNXI_FUNCTION(0x2, "lvds"), /* VN0 */ Ditto about LVDS. > + SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ > + SUNXI_FUNCTION(0x2, "lvds"), /* VP1 */ Ditto about LVDS. > + SUNXI_FUNCTION(0x4, "emac")), /* TXERR */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ > + SUNXI_FUNCTION(0x2, "lvds"), /* VN1 */ Ditto about LVDS. > + SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ > + SUNXI_FUNCTION(0x2, "lvds"), /* VP2 */ Ditto about LVDS. > + SUNXI_FUNCTION(0x4, "emac")), /* MDC */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ > + SUNXI_FUNCTION(0x2, "lvds"), /* VN2 */ Ditto about LVDS. > + SUNXI_FUNCTION(0x4, "emac")), /* MDIO */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ > + SUNXI_FUNCTION(0x2, "lvds")), /* VPC */ Ditto about LVDS. > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ > + SUNXI_FUNCTION(0x2, "lvds")), /* VNC */ Ditto about LVDS. > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */ > + SUNXI_FUNCTION(0x2, "lvds")), /* VP3 */ Ditto about LVDS. > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ > + SUNXI_FUNCTION(0x2, "lvds")), /* VN3 */ Ditto about LVDS. > /* Hole */ > SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), > SUNXI_FUNCTION(0x0, "gpio_in"), > @@ -291,34 +489,91 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { > SUNXI_FUNCTION(0x1, "gpio_out"), > SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ > SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ > + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13), > + PINCTRL_SUN8I_V3, > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2s"), /* DIN */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ > }; > > -static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; > +static const unsigned int sun8i_v3_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; > > -static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { > - .pins = sun8i_v3s_pins, > - .npins = ARRAY_SIZE(sun8i_v3s_pins), > +static const struct sunxi_pinctrl_desc sun8i_v3_v3s_pinctrl_data = { > + .pins = sun8i_v3_v3s_pins, > + .npins = ARRAY_SIZE(sun8i_v3_v3s_pins), > .irq_banks = 2, > - .irq_bank_map = sun8i_v3s_pinctrl_irq_bank_map, > + .irq_bank_map = sun8i_v3_v3s_pinctrl_irq_bank_map, > .irq_read_needs_mux = true > }; > > -static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) > +static int sun8i_v3_v3s_pinctrl_probe(struct platform_device *pdev) > { > - return sunxi_pinctrl_init(pdev, > - &sun8i_v3s_pinctrl_data); > + unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); > + > + return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3_v3s_pinctrl_data, > + variant); > } > > -static const struct of_device_id sun8i_v3s_pinctrl_match[] = { > - { .compatible = "allwinner,sun8i-v3s-pinctrl", }, > - {} > +static const struct of_device_id sun8i_v3_v3s_pinctrl_match[] = { > + { > + .compatible = "allwinner,sun8i-v3-pinctrl", > + .data = (void *)PINCTRL_SUN8I_V3 > + }, > + { > + .compatible = "allwinner,sun8i-v3s-pinctrl", > + .data = (void *)PINCTRL_SUN8I_V3S > + }, > + { }, > }; > > -static struct platform_driver sun8i_v3s_pinctrl_driver = { > - .probe = sun8i_v3s_pinctrl_probe, > +static struct platform_driver sun8i_v3_v3s_pinctrl_driver = { > + .probe = sun8i_v3_v3s_pinctrl_probe, > .driver = { > - .name = "sun8i-v3s-pinctrl", > - .of_match_table = sun8i_v3s_pinctrl_match, > + .name = "sun8i-v3-v3s-pinctrl", > + .of_match_table = sun8i_v3_v3s_pinctrl_match, > }, > }; > -builtin_platform_driver(sun8i_v3s_pinctrl_driver); > +builtin_platform_driver(sun8i_v3_v3s_pinctrl_driver); > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > index ee15ab067b5f..cfff6b02ddae 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h > @@ -94,6 +94,8 @@ > #define PINCTRL_SUN4I_A10 BIT(6) > #define PINCTRL_SUN7I_A20 BIT(7) > #define PINCTRL_SUN8I_R40 BIT(8) > +#define PINCTRL_SUN8I_V3 BIT(9) > +#define PINCTRL_SUN8I_V3S BIT(10) > > struct sunxi_desc_function { > unsigned long variant; > -- > 2.18.1 >
Hi, Le mardi 12 mars 2019 à 23:45 +0800, Icenowy Zheng a écrit : > > 于 2019年3月12日 GMT+08:00 下午11:36:54, Maxime Ripard <maxime.ripard@bootlin.com> 写到: > > On Tue, Mar 12, 2019 at 11:22:46PM +0800, Icenowy Zheng wrote: > > > Introduce the GPIO pins that is only available on V3 (not on V3s) to > > the > > > V3 pinctrl driver. > > > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > --- > > > drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c | 291 > > +++++++++++++++++++++-- > > > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + > > > 2 files changed, 275 insertions(+), 18 deletions(-) > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > > index 6704ce8e5e3d..54c210871a95 100644 > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > > @@ -1,5 +1,5 @@ > > > /* > > > - * Allwinner V3s SoCs pinctrl driver. > > > + * Allwinner V3/V3s SoCs pinctrl driver. > > > * > > > * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> > > > * > > > @@ -23,7 +23,7 @@ > > > > > > #include "pinctrl-sunxi.h" > > > > > > -static const struct sunxi_desc_pin sun8i_v3s_pins[] = { > > > +static const struct sunxi_desc_pin sun8i_v3_v3s_pins[] = { > > > > I'm not sure all that remaining is worth it to be honest. It adds a > > lot of noise for no particular reason (and the same goes for renaming > > the file itself) > > Maybe keeping names is okay "for historial reasons". > > In fact I want to keep them. My two cents about this: kernel development is plagued by the unability to rename and rework things as soon as backward compatibility is involved. I believe that renaming and reworking things is quite a good thing to do when it leads to a situation that is easier to understand and makes more sense. In this case, I don't see any blockers that would prevent us from doing this, so I am strongly in favor of it. I really don't see how increased noise and "historical reasons" make up for better clarity. Cheers, Paul > > Maxime > > -- > 使用 K-9 Mail 发送自我的Android设备。 >
On Mon, Mar 18, 2019 at 12:05:12PM +0100, Paul Kocialkowski wrote: > Hi, > > Le mardi 12 mars 2019 à 23:45 +0800, Icenowy Zheng a écrit : > > > > 于 2019年3月12日 GMT+08:00 下午11:36:54, Maxime Ripard <maxime.ripard@bootlin.com> 写到: > > > On Tue, Mar 12, 2019 at 11:22:46PM +0800, Icenowy Zheng wrote: > > > > Introduce the GPIO pins that is only available on V3 (not on V3s) to > > > the > > > > V3 pinctrl driver. > > > > > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > > --- > > > > drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c | 291 > > > +++++++++++++++++++++-- > > > > drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + > > > > 2 files changed, 275 insertions(+), 18 deletions(-) > > > > > > > > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > > b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > > > index 6704ce8e5e3d..54c210871a95 100644 > > > > --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > > > +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3.c > > > > @@ -1,5 +1,5 @@ > > > > /* > > > > - * Allwinner V3s SoCs pinctrl driver. > > > > + * Allwinner V3/V3s SoCs pinctrl driver. > > > > * > > > > * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> > > > > * > > > > @@ -23,7 +23,7 @@ > > > > > > > > #include "pinctrl-sunxi.h" > > > > > > > > -static const struct sunxi_desc_pin sun8i_v3s_pins[] = { > > > > +static const struct sunxi_desc_pin sun8i_v3_v3s_pins[] = { > > > > > > I'm not sure all that remaining is worth it to be honest. It adds a > > > lot of noise for no particular reason (and the same goes for renaming > > > the file itself) > > > > Maybe keeping names is okay "for historial reasons". > > > > In fact I want to keep them. > > My two cents about this: kernel development is plagued by the unability > to rename and rework things as soon as backward compatibility is > involved. I believe that renaming and reworking things is quite a good > thing to do when it leads to a situation that is easier to understand > and makes more sense. > > In this case, I don't see any blockers that would prevent us from doing > this, so I am strongly in favor of it. I really don't see how increased > noise and "historical reasons" make up for better clarity. It simplifies the git history, for once, which has the side effect of reducing conflicts too. A second one is: Do you prefer to review patches that have some significant value (like a new feature, a bugfix, a new SoC support, etc) or one that renames files and / or symbols? Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
Hi, Le mardi 12 mars 2019 à 23:22 +0800, Icenowy Zheng a écrit : > The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, > but with more GPIO wired out of the package. > > Add DTSI files for these SoCs. The DTSI file for V3 just replaces the > pinctrl compatible string, and the S3/S3L DTSI files just include the V3 > DTSI file. Note that the V3 has a NMI controller at 1c000d0, that is required for handling the AXP209 interrupts IIRQ. I have no idea whether it's also the case on the V3s/S3/S3L though but it would be good to know. Note that I can totally add support for it when adding support for my V3 device that uses the AXP209 this way. Also, could we get proper compatibles and config options for these new SoCs, since they are distinct from the V3S? Cheers, Paul > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ > arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ > arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ > 3 files changed, 26 insertions(+) > create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi > create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi > create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi > > diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi b/arch/arm/boot/dts/sun8i-s3.dtsi > new file mode 100644 > index 000000000000..0f41a25ecb30 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3.dtsi > @@ -0,0 +1,6 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi > new file mode 100644 > index 000000000000..0f41a25ecb30 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi > @@ -0,0 +1,6 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3.dtsi" > diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi > new file mode 100644 > index 000000000000..6ae8645ade50 > --- /dev/null > +++ b/arch/arm/boot/dts/sun8i-v3.dtsi > @@ -0,0 +1,14 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > + */ > + > +#include "sun8i-v3s.dtsi" > + > +&ccu { > + compatible = "allwinner,sun8i-v3-ccu"; > +}; > + > +&pio { > + compatible = "allwinner,sun8i-v3-pinctrl"; > +}; > -- > 2.18.1 >
于 2019年3月18日 GMT+08:00 下午8:41:32, Paul Kocialkowski <paul.kocialkowski@bootlin.com> 写到: >Hi, > >Le mardi 12 mars 2019 à 23:22 +0800, Icenowy Zheng a écrit : >> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, >> but with more GPIO wired out of the package. >> >> Add DTSI files for these SoCs. The DTSI file for V3 just replaces the >> pinctrl compatible string, and the S3/S3L DTSI files just include the >V3 >> DTSI file. > >Note that the V3 has a NMI controller at 1c000d0, that is required for >handling the AXP209 interrupts IIRQ. I have no idea whether it's also >the case on the V3s/S3/S3L though but it would be good to know. It's not mentioned on the datasheet. If it's present, please send a patch. BTW all V3 series chip share the same die (sun8iw8). Thanks > >Note that I can totally add support for it when adding support for my >V3 device that uses the AXP209 this way. > >Also, could we get proper compatibles and config options for these new >SoCs, since they are distinct from the V3S? > >Cheers, > >Paul > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> --- >> arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ >> arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ >> arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ >> 3 files changed, 26 insertions(+) >> create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi >> create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi >> create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi >> >> diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi >b/arch/arm/boot/dts/sun8i-s3.dtsi >> new file mode 100644 >> index 000000000000..0f41a25ecb30 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-s3.dtsi >> @@ -0,0 +1,6 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3.dtsi" >> diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi >b/arch/arm/boot/dts/sun8i-s3l.dtsi >> new file mode 100644 >> index 000000000000..0f41a25ecb30 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi >> @@ -0,0 +1,6 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3.dtsi" >> diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi >b/arch/arm/boot/dts/sun8i-v3.dtsi >> new file mode 100644 >> index 000000000000..6ae8645ade50 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun8i-v3.dtsi >> @@ -0,0 +1,14 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> >> + */ >> + >> +#include "sun8i-v3s.dtsi" >> + >> +&ccu { >> + compatible = "allwinner,sun8i-v3-ccu"; >> +}; >> + >> +&pio { >> + compatible = "allwinner,sun8i-v3-pinctrl"; >> +}; >> -- >> 2.18.1 >> >-- >Paul Kocialkowski, Bootlin >Embedded Linux and kernel engineering >https://bootlin.com > > >_______________________________________________ >linux-arm-kernel mailing list >linux-arm-kernel@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Hi, Le lundi 18 mars 2019 à 23:15 +0800, Icenowy Zheng a écrit : > > 于 2019年3月18日 GMT+08:00 下午8:41:32, Paul Kocialkowski <paul.kocialkowski@bootlin.com> 写到: > > Hi, > > > > Le mardi 12 mars 2019 à 23:22 +0800, Icenowy Zheng a écrit : > > > The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC, > > > but with more GPIO wired out of the package. > > > > > > Add DTSI files for these SoCs. The DTSI file for V3 just replaces the > > > pinctrl compatible string, and the S3/S3L DTSI files just include the > > V3 > > > DTSI file. > > > > Note that the V3 has a NMI controller at 1c000d0, that is required for > > handling the AXP209 interrupts IIRQ. I have no idea whether it's also > > the case on the V3s/S3/S3L though but it would be good to know. > > It's not mentioned on the datasheet. > > If it's present, please send a patch. Indeed, it is not documented but the block is definitely there (and it shows up in Allwinner's kernel source too). I'll send a patch once these series is merged then! > BTW all V3 series chip share the same die (sun8iw8). Right, so I think it's safe to assume that the controller is there on all of them then. Cheers, Paul > Thanks > > > Note that I can totally add support for it when adding support for my > > V3 device that uses the AXP209 this way. > > > > Also, could we get proper compatibles and config options for these new > > SoCs, since they are distinct from the V3S? > > > > Cheers, > > > > Paul > > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > --- > > > arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++ > > > arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++ > > > arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++ > > > 3 files changed, 26 insertions(+) > > > create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi > > > create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi > > > create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi > > > > > > diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi > > b/arch/arm/boot/dts/sun8i-s3.dtsi > > > new file mode 100644 > > > index 000000000000..0f41a25ecb30 > > > --- /dev/null > > > +++ b/arch/arm/boot/dts/sun8i-s3.dtsi > > > @@ -0,0 +1,6 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > > +/* > > > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > > > + */ > > > + > > > +#include "sun8i-v3.dtsi" > > > diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi > > b/arch/arm/boot/dts/sun8i-s3l.dtsi > > > new file mode 100644 > > > index 000000000000..0f41a25ecb30 > > > --- /dev/null > > > +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi > > > @@ -0,0 +1,6 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > > +/* > > > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > > > + */ > > > + > > > +#include "sun8i-v3.dtsi" > > > diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi > > b/arch/arm/boot/dts/sun8i-v3.dtsi > > > new file mode 100644 > > > index 000000000000..6ae8645ade50 > > > --- /dev/null > > > +++ b/arch/arm/boot/dts/sun8i-v3.dtsi > > > @@ -0,0 +1,14 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > > +/* > > > + * Copyright (C) 2019 Icenowy Zheng <icenowy@aosc.io> > > > + */ > > > + > > > +#include "sun8i-v3s.dtsi" > > > + > > > +&ccu { > > > + compatible = "allwinner,sun8i-v3-ccu"; > > > +}; > > > + > > > +&pio { > > > + compatible = "allwinner,sun8i-v3-pinctrl"; > > > +}; > > > -- > > > 2.18.1 > > > > > -- > > Paul Kocialkowski, Bootlin > > Embedded Linux and kernel engineering > > https://bootlin.com > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Tue, Mar 12, 2019 at 10:24 PM Icenowy Zheng <icenowy@aosc.io> wrote:
> This patchset tries to add support for Allwinner V3/S3L and Sochip S3.
I see there is some review comments on this patch set so I am waiting
for v2.
When we have something Maxime, Rob etc has ACKed, I suggest I merge
the pinctrl stuff into an immutable branch in the pinctrl tree so that it can
be pulled in to ARM SoC if need be (for DTS files to compile for example).
Yours,
Linus Walleij
This patchset tries to add support for Allwinner V3/S3L and Sochip S3. Allwinner V3/V3s/S3L and Sochip S3 share the same die, but with different package. V3 is BGA w/o co-packaged DDR, V3s is QFP w/ DDR2, S3L is BGA w/ DDR2 and S3 is BGA w/ DDR3. (S3 and S3L is compatible for pinout, but because of different DDR, DDR voltage is different between the two variants). Because of the pin count of V3s is restricted due to the package, some pins are not bound on V3s, but they're bound on V3/S3/S3L. Currently the kernel is only prepared for the features available on V3s. This patchset adds the features missing on V3s for using them on V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3L device, the Pine64 Single Cube Computer. The S3/S3L SoM by Sipeed (formerly Lichee Pi), called Lichee Nano Plus, is ongoing. Icenowy Zheng (14): dt-bindings: pinctrl: add missing compatible string for V3s pinctrl: sunxi: rename V3s driver to V3 driver dt-bindings: pinctrl: add compatible string for Allwinner V3 pinctrl pinctrl: sunxi: v3: really introduce support for V3 clk: sunxi-ng: v3s: add the missing PLL_DDR1 dt-bindings: clock: sunxi-ccu: remove bogus + before R40 compatible dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU clk: sunxi-ng: v3s: add Allwinner V3 support dt-bindings: vendor-prefixes: add SoChip dt-bindings: arm: sunxi: add compatible string for V3/S3/S3L SoCs ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2 RX/TX ARM: dts: sun8i: V3/V3s/S3/S3L: add Ethernet support ARM: dts: sun8i: s3l: add support for Pine64 Single Cube Computer .../devicetree/bindings/arm/sunxi.txt | 3 + .../devicetree/bindings/clock/sunxi-ccu.txt | 3 +- .../pinctrl/allwinner,sunxi-pinctrl.txt | 2 + .../devicetree/bindings/vendor-prefixes.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-s3.dtsi | 6 + .../dts/sun8i-s3l-single-cube-computer.dts | 166 ++++++++++ arch/arm/boot/dts/sun8i-s3l.dtsi | 6 + arch/arm/boot/dts/sun8i-v3.dtsi | 27 ++ arch/arm/boot/dts/sun8i-v3s.dtsi | 59 ++++ drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 244 ++++++++++++++- drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 6 +- drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/Makefile | 2 +- ...pinctrl-sun8i-v3s.c => pinctrl-sun8i-v3.c} | 291 ++++++++++++++++-- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 2 + include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 + include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 + 18 files changed, 799 insertions(+), 29 deletions(-) create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi create mode 100644 arch/arm/boot/dts/sun8i-s3l-single-cube-computer.dts create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi rename drivers/pinctrl/sunxi/{pinctrl-sun8i-v3s.c => pinctrl-sun8i-v3.c} (51%)