From patchwork Tue Nov 13 14:48:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 997248 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="ePyRxlVJ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42vVqn3tFyz9s5c for ; Wed, 14 Nov 2018 01:48:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387892AbeKNAqo (ORCPT ); Tue, 13 Nov 2018 19:46:44 -0500 Received: from mail-wm1-f48.google.com ([209.85.128.48]:51424 "EHLO mail-wm1-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387725AbeKNAqo (ORCPT ); Tue, 13 Nov 2018 19:46:44 -0500 Received: by mail-wm1-f48.google.com with SMTP id w7-v6so12201128wmc.1 for ; Tue, 13 Nov 2018 06:48:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=bbY+0AzP+H3yzuk4q47b0ANkXIlf0xE24RY6DaCQYtA=; b=ePyRxlVJITMqp7STi/63B7AW3+0PebDSQeNxXmfy1FFYJg8PH5cBCkNpmG/tRJQiyn 8F8v/PjaxQWOlMwC8aXa6fcRJhHqh5un5fBWM/j4NN89ASdZu4MZlU1Ft/dXeB2YMwdL ztNl+cEFTiok9rFF+zz1s05ZHHzvXxIFfZr0I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=bbY+0AzP+H3yzuk4q47b0ANkXIlf0xE24RY6DaCQYtA=; b=EFWkDcoU99NH8YIPuaR8wt5wXaX97YffeqQiXsJYVRW1s1ffLTnkwYeDyyurSW9w5H M8bsFXv+b3g6DFMJn+5vCRZRVzhBTJ71vuslFrBm8NO1W914IFvGxKyhBYnKULLEITg3 6rVn50T6G8yb6MQluw25m/L+plY3vlpzA7xNR+MSak9Xa/r6yN5sm/vNRz8xQ9OGegfS 3KQEde0XLxcE39mreX3oJoLOIzZFpyeIwFlbWQc16UN95b9oXjDr4t+Oz12KzFPzcLh/ ZeMPX2nsrMNWuPgCl9hR/Ss8NAOrY90E1N2mtTlq/Zxydj1VBcV/elWgjus/TQg+RGiD Yn6g== X-Gm-Message-State: AGRZ1gL4GWlmxB5pbfig+3uH9U/6M1AXFWvnkvRA2jm/clI4YNEN7CRB BNy4gkvSqtcbonbvUTQCqU4Ngg== X-Google-Smtp-Source: AJdET5eKnAdE58e9AXE8q/u2CG6E/c/NWy78fh2QoRQwb15FLvuvFx5vyWHYJn9es0QOJ9xDn/k2gQ== X-Received: by 2002:a1c:b4c1:: with SMTP id d184-v6mr3574811wmf.143.1542120493849; Tue, 13 Nov 2018 06:48:13 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:1088:2b4c:8cab:bca7:b2f2:d2bb]) by smtp.gmail.com with ESMTPSA id s16sm3292020wrt.77.2018.11.13.06.48.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Nov 2018 06:48:13 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH 0/3] Make STM32 interrupt controller use hwspinlock Date: Tue, 13 Nov 2018 15:48:02 +0100 Message-Id: <20181113144805.1054-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series allow to protect STM32 interrupt controller configuration registers with a hwspinlock to avoid conflicting accesses between processors. Benjamin Gaignard (3): dt-bindings: interrupt-controller: stm32: Document hwlock properties irqchip: stm32: protect configuration registers with hwspinlock ARM: dts: stm32: Add hwlock for irqchip on stm32mp157 .../interrupt-controller/st,stm32-exti.txt | 4 +++ arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/irqchip/irq-stm32-exti.c | 36 ++++++++++++++++++---- 3 files changed, 35 insertions(+), 6 deletions(-)