From patchwork Mon Nov 12 15:23:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 996503 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="JM4J2WwD"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42tvgQ4bk0z9s3C for ; Tue, 13 Nov 2018 02:24:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728064AbeKMBRc (ORCPT ); Mon, 12 Nov 2018 20:17:32 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:51638 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727659AbeKMBRc (ORCPT ); Mon, 12 Nov 2018 20:17:32 -0500 Received: by mail-wm1-f67.google.com with SMTP id w7-v6so8892323wmc.1 for ; Mon, 12 Nov 2018 07:23:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=yyvl64X5FbEhFmlfbNEvG6Iy+6IGW5U2Gxn+yiL2vUg=; b=JM4J2WwDaJv7/mGrG8PzE4ZVTExFbQaSrBQ49OkalBJfw7gi0dP1ZomHuuXkm1sY/t FvmiGeuE1wY0pyii8aiTC4ZI2xMcG3QN+e+56zyA0/S7NDKWj1WFkoUqq6mbAiaH0peW NVr3I46lOOkRyx8FeDgtIaCKBPLUqOeD5pcQ4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=yyvl64X5FbEhFmlfbNEvG6Iy+6IGW5U2Gxn+yiL2vUg=; b=fCTNu+GcNKSzxTaxlClJIop7lDdhbiwD/jw4BqJ98Y4bjQDgEKPpSx0mSb7aVWCkgk bHSuI7f5Xigw9V+G5lXLSpC4pgeYajLdNApj3FxSLbljETJca7zo6Vj6JCCKTdV83hbb 2e6I5SUG01igJjRflpkzBhtfU9HtLPg8uhJz7mN8S59gZ8uLbuIRxTcpKzuZM16xkrEy YK466PGDYLNUJuA2cqRm5YJNy00JC8oMW9jMIltcz4tqGTBM/u/DfBtgtzmqrP5hKs0F 0+w0OjSxbawmHCsPUcTlND0Yqi3CZ437Q8WvanJo0hcA4R0eI3eesRbYdtpcjh2pwZ4C iFzg== X-Gm-Message-State: AGRZ1gKk/3Z60pnNMHDeKltKy+YNZPRKayYMIf+LFYNLAUVvn90QoPg0 5DwItWFxNmxG+gK1h/oYtyf2uw== X-Google-Smtp-Source: AJdET5dwKqifJeOi6AfR1btP9CVim7x33pesNQnj5j/q0N+dOFNVQmj+Lo0Y6ynVtggakHzKBv+0eA== X-Received: by 2002:a1c:7cc:: with SMTP id 195-v6mr40989wmh.139.1542036228751; Mon, 12 Nov 2018 07:23:48 -0800 (PST) Received: from lmecxl0911.lme.st.com ([2a04:cec0:105e:a8d5:7c2c:2737:d373:11ee]) by smtp.gmail.com with ESMTPSA id t82-v6sm11192849wme.30.2018.11.12.07.23.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Nov 2018 07:23:48 -0800 (PST) From: Benjamin Gaignard X-Google-Original-From: Benjamin Gaignard To: ohad@wizery.com, bjorn.andersson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, alexandre.torgue@st.com Cc: linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, Benjamin Gaignard Subject: [PATCH v3 0/4] Add support of STM32 hwspinlock Date: Mon, 12 Nov 2018 16:23:38 +0100 Message-Id: <20181112152342.6561-1-benjamin.gaignard@st.com> X-Mailer: git-send-email 2.15.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This serie adds the support of the hardware semaphore block for stm32mp1 SoC. version 3: - fix clock name in properties description. - use postcore_initcall() instead of module_platform_driver() version 2: - fix comments done by Bjorn about clock naming, license terms in header, alphabetic ordering in Makefile and Kconfig and remove function - Do not push test module in this version while waiting for feedbacks about it Benjamin Gaignard (4): dt-bindings: hwlock: Document STM32 hwspinlock bindings hwspinlock: add STM32 hwspinlock device ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC ARM: dts: stm32: enable hwspinlock on stm32mp157c-ed1 .../bindings/hwlock/st,stm32-hwspinlock.txt | 23 +++ arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 + arch/arm/boot/dts/stm32mp157c.dtsi | 9 ++ drivers/hwspinlock/Kconfig | 9 ++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/stm32_hwspinlock.c | 156 +++++++++++++++++++++ 6 files changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt create mode 100644 drivers/hwspinlock/stm32_hwspinlock.c