From patchwork Sat Oct 20 13:50:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 987199 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="hLHJWG8A"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42ckgz4xZ9z9sDX for ; Sun, 21 Oct 2018 00:50:39 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727483AbeJTWBI (ORCPT ); Sat, 20 Oct 2018 18:01:08 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:50331 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727382AbeJTWBH (ORCPT ); Sat, 20 Oct 2018 18:01:07 -0400 Received: by mail-wm1-f65.google.com with SMTP id i8-v6so6060990wmg.0 for ; Sat, 20 Oct 2018 06:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=LlbabcyQd1j/wICcOq6oJhFka402EV/LPkkjkVKQIUg=; b=hLHJWG8ATbbUnsr+VLWBYj85dk2wCVNErURhl2WpGrKPNcu84h0I+Po/hAOxAzRcXh q8uK6Aut6yUPuEKh2KOShDrhH+LPaBo0H+ae4E6humcFaeCJ5wzJ5UDorW/XnqHY8KUZ L2FNg2QPFtTiaMEDExRD8mgCsjvpbrumEPj8B1dxR8yL/+1/+fCZj2xd/KPRX18Tgcvg YAFpoMucVxUsgXYoSznTVvENRNTRVL1uQrXM79ADktBh6I0dQLbOCuK15snY9fPkhLvG phxh5Ss2X2WnDA2HRGpucmCd3Njp36ICbzZBaitx6qGs7Ov3Gi2rpkR1HgB/8POQAhEu sb2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=LlbabcyQd1j/wICcOq6oJhFka402EV/LPkkjkVKQIUg=; b=tHy8kJyQp5BOAsSCsDhkcKSrzXSDEY/lXh4N7QHBjcdLpnCMYRMn2c3HAMQo59HDYM 5f6yEQwdt+tUMDWSrCpawZzvYVUOs89crfaGo+o9TEAcEXNc5//qZsWoEzpVcBcc/oJ+ IhiyG19GjRmz9j24EJS8dVRazr2UvbQQOLsq0s6woQMpl6cqSCnAzF9Zex7jS/lmanv3 3S11AY7okhyYKTf6gpLWtDgMoU+T2KEwgOdAyC86ddEkyO04PvEE8W6r6RR09tw06G15 it77ge/7PQvOIjWiaj0U9lT3nPZoTYbPaagAfR6BzJiqsDD2hxS4k9xXWhEU5tEwyWT7 A5Ug== X-Gm-Message-State: ABuFfojxCBCndARp+dP1hugUoCBZUPU+t0vuSSshOfO2bEb2Me0ov1Va 1YD8gXiRbBIqunflLzBfqiNO3g== X-Google-Smtp-Source: ACcGV63StSgMHPhXytIVulh7lSgv9KF4DTrx0iLRWBJmnl1yLvDiNn6Fyc7tov+0pZqHpU2MvLKHuA== X-Received: by 2002:a1c:1fcd:: with SMTP id f196-v6mr8968379wmf.19.1540043433471; Sat, 20 Oct 2018 06:50:33 -0700 (PDT) Received: from viisi.sifive.com ([37.152.39.96]) by smtp.gmail.com with ESMTPSA id o4-v6sm16906615wrj.45.2018.10.20.06.50.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 20 Oct 2018 06:50:32 -0700 (PDT) From: Paul Walmsley To: linux-clk@vger.kernel.org, devicetree@vger.kernel.org Cc: Paul Walmsley , Michael Turquette , Stephen Boyd , Albert Ou , "Wesley W . Terpstra" , Palmer Dabbelt , Megan Wachs , Rob Herring , Mark Rutland , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] clk: add driver for the SiFive FU540 PRCI and PLLs it controls Date: Sat, 20 Oct 2018 06:50:21 -0700 Message-Id: <20181020135024.28573-1-paul.walmsley@sifive.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a driver for the SiFive FU540 PRCI IP block, which handles clock and some device reset control for the SiFive FU540 chip. Also add a driver- independent library for the Analog Bits Wide-Range PLL (WRPLL), used by the PRCI driver to monitor and control the WRPLL instances on the FU540 chip. It's been a long time since I've worked on Linux clock code, so Mike & Stephen, I'd appreciate a close look at the PRCI driver to make sure what it's doing makes sense. Boot-tested on a SiFive HiFive Unleashed board. COREPLL rate changes and notification were also tested on the same board. This second version corrects the DT binding documentation patch; an out-of-date version of that patch was sent with the first version. This patch series is also available at: https://github.com/sifive/riscv-linux/tree/dev/paulw/prci-v4.19-rc7 Paul Walmsley (3): clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver clk: sifive: add a driver for the SiFive FU540 PRCI IP block .../bindings/clock/sifive/fu540-prci.txt | 43 ++ MAINTAINERS | 6 + drivers/clk/Kconfig | 2 + drivers/clk/Makefile | 2 + drivers/clk/analogbits/Kconfig | 3 + drivers/clk/analogbits/Makefile | 2 + drivers/clk/analogbits/wrpll-cln28hpc.c | 387 +++++++++++ drivers/clk/sifive/Kconfig | 18 + drivers/clk/sifive/Makefile | 1 + drivers/clk/sifive/fu540-prci.c | 634 ++++++++++++++++++ include/linux/clk/analogbits-wrpll-cln28hpc.h | 99 +++ include/linux/clk/sifive-fu540-prci.h | 27 + 12 files changed, 1224 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt create mode 100644 drivers/clk/analogbits/Kconfig create mode 100644 drivers/clk/analogbits/Makefile create mode 100644 drivers/clk/analogbits/wrpll-cln28hpc.c create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 include/linux/clk/analogbits-wrpll-cln28hpc.h create mode 100644 include/linux/clk/sifive-fu540-prci.h Cc: Michael Turquette Cc: Stephen Boyd Cc: Albert Ou Cc: Wesley W. Terpstra Cc: Palmer Dabbelt Cc: Megan Wachs Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-clk@vger.kernel.org