| Message ID | 20181004122855.22981-1-icenowy@aosc.io |
|---|---|
| Headers | show |
| Series | Allwinner H6 USB support | expand |
On Thu, Oct 4, 2018 at 8:29 PM Icenowy Zheng <icenowy@aosc.io> wrote: > > This patchset introduces support for the USB ports (both USB2 and USB3) > on the Allwinner H6 SoC. > > The first 6 PATCHes are the USB2 part, and the latter 4 PATCHes are the > USB3 part. > > PATCH 1, 2, 3, 7, 8 should go through the PHY tree, and the remaining > patches should go through the armsoc tree via sunxi tree. > > Icenowy Zheng (10): > dt-bindings: phy: add binding for Allwinner H6 USB2 PHY > phy: sun4i-usb: add support for missing USB PHY index > phy: sun4i-usb: add support for H6 USB2 PHY > arm64: allwinner: dts: h6: add USB2-related device nodes > arm64: allwinner: dts: h6: add USB Vbus regulator > arm64: allwinner: dts: h6: enable USB2 on Pine H64 > dt-bindings: phy: add binding for Allwinner USB3 PHY > phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC > arm64: allwinner: dts: h6: add USB3 device nodes > arm64: allwinner: dts: h6: enable USB3 port on Pine H64 Tested-by: Chen-Yu Tsai <wens@csie.org>
在 2018-10-04四的 20:28 +0800，Icenowy Zheng写道： > The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner > SoCs, > with some USB0 quirk like A83T and PHY index 1/2 missing. > > Add support for it. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Reviewed-by: Chen-Yu Tsai <wens@csie.org> Excuse me. Kishon, could you check PATCH 1~3 and queue them? Even if USB3 support is pending, USB2 support will still be useful, and they're independent. > --- > No changes in v4. > > Changes in v3: > - Added Chen-Yu's Review tag. > > drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c > b/drivers/phy/allwinner/phy-sun4i-usb.c > index 881078ff73f6..ae16854a770a 100644 > --- a/drivers/phy/allwinner/phy-sun4i-usb.c > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c > @@ -115,6 +115,7 @@ enum sun4i_usb_phy_type { > sun8i_r40_phy, > sun8i_v3s_phy, > sun50i_a64_phy, > + sun50i_h6_phy, > }; > > struct sun4i_usb_phy_cfg { > @@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy *_phy) > return ret; > } > > - if (data->cfg->type == sun8i_a83t_phy) { > + if (data->cfg->type == sun8i_a83t_phy || > + data->cfg->type == sun50i_h6_phy) { > if (phy->index == 0) { > val = readl(data->base + data->cfg- > >phyctl_offset); > val |= PHY_CTL_VBUSVLDEXT; > @@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy *_phy) > struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); > > if (phy->index == 0) { > - if (data->cfg->type == sun8i_a83t_phy) { > + if (data->cfg->type == sun8i_a83t_phy || > + data->cfg->type == sun50i_h6_phy) { > void __iomem *phyctl = data->base + > data->cfg->phyctl_offset; > > @@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg > sun50i_a64_cfg = { > .phy0_dual_route = true, > }; > > +static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { > + .num_phys = 4, > + .type = sun50i_h6_phy, > + .disc_thresh = 3, > + .phyctl_offset = REG_PHYCTL_A33, > + .dedicated_clocks = true, > + .enable_pmu_unk1 = true, > + .phy0_dual_route = true, > + .missing_phys = BIT(1) | BIT(2), > +}; > + > static const struct of_device_id sun4i_usb_phy_of_match[] = { > { .compatible = "allwinner,sun4i-a10-usb-phy", .data = > &sun4i_a10_cfg }, > { .compatible = "allwinner,sun5i-a13-usb-phy", .data = > &sun5i_a13_cfg }, > @@ -972,6 +986,7 @@ static const struct of_device_id > sun4i_usb_phy_of_match[] = { > { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = > &sun8i_v3s_cfg }, > { .compatible = "allwinner,sun50i-a64-usb-phy", > .data = &sun50i_a64_cfg}, > + { .compatible = "allwinner,sun50i-h6-usb-phy", .data = > &sun50i_h6_cfg }, > { }, > }; > MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
On 02/11/18 2:11 PM, Icenowy Zheng wrote: > 在 2018-10-04四的 20:28 +0800，Icenowy Zheng写道： >> The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner >> SoCs, >> with some USB0 quirk like A83T and PHY index 1/2 missing. >> >> Add support for it. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> Reviewed-by: Chen-Yu Tsai <wens@csie.org> > > Excuse me. > > Kishon, could you check PATCH 1~3 and queue them? > > Even if USB3 support is pending, USB2 support will still be useful, and > they're independent. I'll queue once -rc1 is tagged. Thanks Kishon > >> --- >> No changes in v4. >> >> Changes in v3: >> - Added Chen-Yu's Review tag. >> >> drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++-- >> 1 file changed, 17 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c >> b/drivers/phy/allwinner/phy-sun4i-usb.c >> index 881078ff73f6..ae16854a770a 100644 >> --- a/drivers/phy/allwinner/phy-sun4i-usb.c >> +++ b/drivers/phy/allwinner/phy-sun4i-usb.c >> @@ -115,6 +115,7 @@ enum sun4i_usb_phy_type { >> sun8i_r40_phy, >> sun8i_v3s_phy, >> sun50i_a64_phy, >> + sun50i_h6_phy, >> }; >> >> struct sun4i_usb_phy_cfg { >> @@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy *_phy) >> return ret; >> } >> >> - if (data->cfg->type == sun8i_a83t_phy) { >> + if (data->cfg->type == sun8i_a83t_phy || >> + data->cfg->type == sun50i_h6_phy) { >> if (phy->index == 0) { >> val = readl(data->base + data->cfg- >>> phyctl_offset); >> val |= PHY_CTL_VBUSVLDEXT; >> @@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy *_phy) >> struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); >> >> if (phy->index == 0) { >> - if (data->cfg->type == sun8i_a83t_phy) { >> + if (data->cfg->type == sun8i_a83t_phy || >> + data->cfg->type == sun50i_h6_phy) { >> void __iomem *phyctl = data->base + >> data->cfg->phyctl_offset; >> >> @@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg >> sun50i_a64_cfg = { >> .phy0_dual_route = true, >> }; >> >> +static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { >> + .num_phys = 4, >> + .type = sun50i_h6_phy, >> + .disc_thresh = 3, >> + .phyctl_offset = REG_PHYCTL_A33, >> + .dedicated_clocks = true, >> + .enable_pmu_unk1 = true, >> + .phy0_dual_route = true, >> + .missing_phys = BIT(1) | BIT(2), >> +}; >> + >> static const struct of_device_id sun4i_usb_phy_of_match[] = { >> { .compatible = "allwinner,sun4i-a10-usb-phy", .data = >> &sun4i_a10_cfg }, >> { .compatible = "allwinner,sun5i-a13-usb-phy", .data = >> &sun5i_a13_cfg }, >> @@ -972,6 +986,7 @@ static const struct of_device_id >> sun4i_usb_phy_of_match[] = { >> { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = >> &sun8i_v3s_cfg }, >> { .compatible = "allwinner,sun50i-a64-usb-phy", >> .data = &sun50i_a64_cfg}, >> + { .compatible = "allwinner,sun50i-h6-usb-phy", .data = >> &sun50i_h6_cfg }, >> { }, >> }; >> MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match); >
在 2018-11-02五的 14:13 +0530，Kishon Vijay Abraham I写道： > > On 02/11/18 2:11 PM, Icenowy Zheng wrote: > > 在 2018-10-04四的 20:28 +0800，Icenowy Zheng写道： > > > The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner > > > SoCs, > > > with some USB0 quirk like A83T and PHY index 1/2 missing. > > > > > > Add support for it. > > > > > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > > Reviewed-by: Chen-Yu Tsai <wens@csie.org> > > > > Excuse me. > > > > Kishon, could you check PATCH 1~3 and queue them? > > > > Even if USB3 support is pending, USB2 support will still be useful, > > and > > they're independent. > > I'll queue once -rc1 is tagged. Ping. 4.20-rc1 is out now. > > Thanks > Kishon > > > > --- > > > No changes in v4. > > > > > > Changes in v3: > > > - Added Chen-Yu's Review tag. > > > > > > drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++-- > > > 1 file changed, 17 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c > > > b/drivers/phy/allwinner/phy-sun4i-usb.c > > > index 881078ff73f6..ae16854a770a 100644 > > > --- a/drivers/phy/allwinner/phy-sun4i-usb.c > > > +++ b/drivers/phy/allwinner/phy-sun4i-usb.c > > > @@ -115,6 +115,7 @@ enum sun4i_usb_phy_type { > > > sun8i_r40_phy, > > > sun8i_v3s_phy, > > > sun50i_a64_phy, > > > + sun50i_h6_phy, > > > }; > > > > > > struct sun4i_usb_phy_cfg { > > > @@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy > > > *_phy) > > > return ret; > > > } > > > > > > - if (data->cfg->type == sun8i_a83t_phy) { > > > + if (data->cfg->type == sun8i_a83t_phy || > > > + data->cfg->type == sun50i_h6_phy) { > > > if (phy->index == 0) { > > > val = readl(data->base + data->cfg- > > > > phyctl_offset); > > > val |= PHY_CTL_VBUSVLDEXT; > > > @@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy > > > *_phy) > > > struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy); > > > > > > if (phy->index == 0) { > > > - if (data->cfg->type == sun8i_a83t_phy) { > > > + if (data->cfg->type == sun8i_a83t_phy || > > > + data->cfg->type == sun50i_h6_phy) { > > > void __iomem *phyctl = data->base + > > > data->cfg->phyctl_offset; > > > > > > @@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg > > > sun50i_a64_cfg = { > > > .phy0_dual_route = true, > > > }; > > > > > > +static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = { > > > + .num_phys = 4, > > > + .type = sun50i_h6_phy, > > > + .disc_thresh = 3, > > > + .phyctl_offset = REG_PHYCTL_A33, > > > + .dedicated_clocks = true, > > > + .enable_pmu_unk1 = true, > > > + .phy0_dual_route = true, > > > + .missing_phys = BIT(1) | BIT(2), > > > +}; > > > + > > > static const struct of_device_id sun4i_usb_phy_of_match[] = { > > > { .compatible = "allwinner,sun4i-a10-usb-phy", .data = > > > &sun4i_a10_cfg }, > > > { .compatible = "allwinner,sun5i-a13-usb-phy", .data = > > > &sun5i_a13_cfg }, > > > @@ -972,6 +986,7 @@ static const struct of_device_id > > > sun4i_usb_phy_of_match[] = { > > > { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = > > > &sun8i_v3s_cfg }, > > > { .compatible = "allwinner,sun50i-a64-usb-phy", > > > .data = &sun50i_a64_cfg}, > > > + { .compatible = "allwinner,sun50i-h6-usb-phy", .data = > > > &sun50i_h6_cfg }, > > > { }, > > > }; > > > MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match); > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
在 2018-10-04四的 20:28 +0800，Icenowy Zheng写道： > Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also > controlled). > > Add a driver for it. > > The register operations in this driver is mainly extracted from the > BSP > USB3 driver. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Reviewed-by: Chen-Yu Tsai <wens@csie.org> Kishon, I see this patch is picked to linux-next, however this patch is not in the stage that can be picked, because for the Vbus of USB3 PHY Rob Herring still have some problems. Could you remove PATCH 7 and 8 in this patchset now? Thanks! > --- > Changes in v4: > - Added support for vbus-supply property. > > Changes in v3: > - Dropped USB_SUPPORT dependency. > - Added Chen-Yu's Review tag. > > No changes in v2, v1. > > drivers/phy/allwinner/Kconfig | 12 ++ > drivers/phy/allwinner/Makefile | 1 + > drivers/phy/allwinner/phy-sun50i-usb3.c | 239 > ++++++++++++++++++++++++ > 3 files changed, 252 insertions(+) > create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c > > diff --git a/drivers/phy/allwinner/Kconfig > b/drivers/phy/allwinner/Kconfig > index cdc1e745ba47..064096e6a4e5 100644 > --- a/drivers/phy/allwinner/Kconfig > +++ b/drivers/phy/allwinner/Kconfig > @@ -29,3 +29,15 @@ config PHY_SUN9I_USB > sun9i SoCs. > > This driver controls each individual USB 2 host PHY. > + > +config PHY_SUN50I_USB3 > + tristate "Allwinner sun50i SoC USB3 PHY driver" > + depends on ARCH_SUNXI && HAS_IOMEM && OF > + depends on RESET_CONTROLLER > + select USB_COMMON > + select GENERIC_PHY > + help > + Enable this to support the USB3.0-capable transceiver that is > + part of some Allwinner sun50i SoCs. > + > + This driver controls each individual USB 2+3 host PHY combo. > diff --git a/drivers/phy/allwinner/Makefile > b/drivers/phy/allwinner/Makefile > index 8605529c01a1..a8d01e9073c2 100644 > --- a/drivers/phy/allwinner/Makefile > +++ b/drivers/phy/allwinner/Makefile > @@ -1,2 +1,3 @@ > obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o > obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o > +obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o > diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c > b/drivers/phy/allwinner/phy-sun50i-usb3.c > new file mode 100644 > index 000000000000..70c299c01c3e > --- /dev/null > +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c > @@ -0,0 +1,239 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Allwinner sun50i(H6) USB 3.0 phy driver > + * > + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> > + * > + * Based on phy-sun9i-usb.c, which is: > + * > + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org> > + * > + * Based on code from Allwinner BSP, which is: > + * > + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/io.h> > +#include <linux/module.h> > +#include <linux/phy/phy.h> > +#include <linux/usb/of.h> > +#include <linux/platform_device.h> > +#include <linux/regulator/consumer.h> > +#include <linux/reset.h> > + > +/* Interface Status and Control Registers */ > +#define SUNXI_ISCR 0x00 > +#define SUNXI_PIPE_CLOCK_CONTROL 0x14 > +#define SUNXI_PHY_TUNE_LOW 0x18 > +#define SUNXI_PHY_TUNE_HIGH 0x1c > +#define SUNXI_PHY_EXTERNAL_CONTROL 0x20 > + > +/* USB2.0 Interface Status and Control Register */ > +#define SUNXI_ISCR_FORCE_VBUS (3 << 12) > + > +/* PIPE Clock Control Register */ > +#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) > + > +/* PHY External Control Register */ > +#define SUNXI_PEC_EXTERN_VBUS (3 << 1) > +#define SUNXI_PEC_SSC_EN (1 << 24) > +#define SUNXI_PEC_REF_SSP_EN (1 << 26) > + > +/* PHY Tune High Register */ > +#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) > +#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) > +#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) > +#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) > +#define SUNXI_TX_SWING_FULL(n) ((n) << 6) > +#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) > +#define SUNXI_LOS_BIAS(n) ((n) << 3) > +#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) > +#define SUNXI_TXVBOOSTLVL(n) ((n) << 0) > +#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2) > + > +struct sun50i_usb3_phy { > + struct phy *phy; > + void __iomem *regs; > + struct reset_control *reset; > + struct clk *clk; > + bool regulator_on; > + struct regulator *vbus; > +}; > + > +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy) > +{ > + u32 val; > + > + val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); > + val |= SUNXI_PEC_EXTERN_VBUS; > + val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; > + writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); > + > + val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); > + val |= SUNXI_PCC_PIPE_CLK_OPEN; > + writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); > + > + val = readl(phy->regs + SUNXI_ISCR); > + val |= SUNXI_ISCR_FORCE_VBUS; > + writel(val, phy->regs + SUNXI_ISCR); > + > + /* > + * All the magic numbers written to the PHY_TUNE_{LOW_HIGH} > + * registers are directly taken from the BSP USB3 driver from > + * Allwiner. > + */ > + writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); > + > + val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); > + val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | > + SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | > + SUNXI_TX_DEEMPH_3P5DB_MASK); > + val |= SUNXI_TXVBOOSTLVL(0x7); > + val |= SUNXI_LOS_BIAS(0x7); > + val |= SUNXI_TX_SWING_FULL(0x55); > + val |= SUNXI_TX_DEEMPH_6DB(0x20); > + val |= SUNXI_TX_DEEMPH_3P5DB(0x15); > + writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); > +} > + > +static int sun50i_usb3_phy_init(struct phy *_phy) > +{ > + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); > + int ret; > + > + ret = clk_prepare_enable(phy->clk); > + if (ret) > + goto err_clk; > + > + ret = reset_control_deassert(phy->reset); > + if (ret) > + goto err_reset; > + > + sun50i_usb3_phy_open(phy); > + return 0; > + > +err_reset: > + clk_disable_unprepare(phy->clk); > + > +err_clk: > + return ret; > +} > + > +static int sun50i_usb3_phy_exit(struct phy *_phy) > +{ > + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); > + > + reset_control_assert(phy->reset); > + clk_disable_unprepare(phy->clk); > + > + return 0; > +} > + > +static int sun50i_usb3_phy_power_on(struct phy *_phy) > +{ > + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); > + int ret; > + > + if (!phy->vbus || phy->regulator_on) > + return 0; > + > + ret = regulator_enable(phy->vbus); > + if (ret) > + return ret; > + > + phy->regulator_on = true; > + > + return 0; > +} > + > +static int sun50i_usb3_phy_power_off(struct phy *_phy) > +{ > + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); > + > + if (!phy->vbus || !phy->regulator_on) > + return 0; > + > + regulator_disable(phy->vbus); > + phy->regulator_on = false; > + > + return 0; > +} > + > +static const struct phy_ops sun50i_usb3_phy_ops = { > + .init = sun50i_usb3_phy_init, > + .exit = sun50i_usb3_phy_exit, > + .power_on = sun50i_usb3_phy_power_on, > + .power_off = sun50i_usb3_phy_power_off, > + .owner = THIS_MODULE, > +}; > + > +static int sun50i_usb3_phy_probe(struct platform_device *pdev) > +{ > + struct sun50i_usb3_phy *phy; > + struct device *dev = &pdev->dev; > + struct phy_provider *phy_provider; > + struct resource *res; > + > + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); > + if (!phy) > + return -ENOMEM; > + > + phy->clk = devm_clk_get(dev, NULL); > + if (IS_ERR(phy->clk)) { > + dev_err(dev, "failed to get phy clock\n"); > + return PTR_ERR(phy->clk); > + } > + > + phy->reset = devm_reset_control_get(dev, NULL); > + if (IS_ERR(phy->reset)) { > + dev_err(dev, "failed to get reset control\n"); > + return PTR_ERR(phy->reset); > + } > + > + phy->vbus = devm_regulator_get_optional(dev, "vbus"); > + if (IS_ERR(phy->vbus)) { > + if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) { > + dev_err(dev, "Couldn't get vbus regulator... > Deferring probe\n"); > + return -EPROBE_DEFER; > + } > + > + phy->vbus = NULL; > + } > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + phy->regs = devm_ioremap_resource(dev, res); > + if (IS_ERR(phy->regs)) > + return PTR_ERR(phy->regs); > + > + phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops); > + if (IS_ERR(phy->phy)) { > + dev_err(dev, "failed to create PHY\n"); > + return PTR_ERR(phy->phy); > + } > + > + phy_set_drvdata(phy->phy, phy); > + phy_provider = devm_of_phy_provider_register(dev, > of_phy_simple_xlate); > + > + return PTR_ERR_OR_ZERO(phy_provider); > +} > + > +static const struct of_device_id sun50i_usb3_phy_of_match[] = { > + { .compatible = "allwinner,sun50i-h6-usb3-phy" }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match); > + > +static struct platform_driver sun50i_usb3_phy_driver = { > + .probe = sun50i_usb3_phy_probe, > + .driver = { > + .of_match_table = sun50i_usb3_phy_of_match, > + .name = "sun50i-usb3-phy", > + } > +}; > +module_platform_driver(sun50i_usb3_phy_driver); > + > +MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver"); > +MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); > +MODULE_LICENSE("GPL");
Hi, On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote: > > Allwinner H6 has two USB2 ports, one OTG and one host-only. > > Add device tree nodes related to them. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > Reviewed-by: Chen-Yu Tsai <wens@csie.org> > --- > No changes in v4. > > Changes in v3: > - Removed the wrongly introduced usb3phy node. > - Added Chen-Yu's Review tag. > > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81 ++++++++++++++++++++ > 1 file changed, 81 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > index 040828d2e2c0..3d60af6cb3ae 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > @@ -258,6 +258,87 @@ > status = "disabled"; > }; > > + usb2otg: usb@5100000 { > + compatible = "allwinner,sun8i-a33-musb"; I added an SoC-specific compatible: "allwinner,sun50i-h6-musb". I'm also curious as to whether the MUSB controller was tested or not, since Allwinner now has EHCI/OHCI host pairs for host mode, and the Pine H64 only does host mode. > + reg = <0x05100000 0x0400>; > + clocks = <&ccu CLK_BUS_OTG>; > + resets = <&ccu RST_BUS_OTG>; > + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "mc"; > + phys = <&usb2phy 0>; > + phy-names = "usb"; > + extcon = <&usb2phy 0>; > + status = "disabled"; > + }; > + > + usb2phy: phy@5100400 { > + compatible = "allwinner,sun50i-h6-usb-phy"; > + reg = <0x05100400 0x14>, > + <0x05101800 0x4>, > + <0x05311800 0x4>; > + reg-names = "phy_ctrl", > + "pmu0", > + "pmu3"; > + clocks = <&ccu CLK_USB_PHY0>, > + <&ccu CLK_USB_PHY3>; > + clock-names = "usb0_phy", > + "usb3_phy"; > + resets = <&ccu RST_USB_PHY0>, > + <&ccu RST_USB_PHY3>; > + reset-names = "usb0_reset", > + "usb3_reset"; > + status = "disabled"; > + #phy-cells = <1>; > + }; > + > + ehci0: usb@5101000 { > + compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; > + reg = <0x05101000 0x100>; > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_BUS_EHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>, > + <&ccu RST_BUS_EHCI0>; > + status = "disabled"; > + }; > + > + ohci0: usb@5101400 { > + compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; > + reg = <0x05101400 0x100>; > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI0>, > + <&ccu CLK_USB_OHCI0>; > + resets = <&ccu RST_BUS_OHCI0>; > + status = "disabled"; > + }; > + > + ehci3: usb@5311000 { > + compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; > + reg = <0x05311000 0x100>; > + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI3>, > + <&ccu CLK_BUS_EHCI3>, > + <&ccu CLK_USB_OHCI3>; > + resets = <&ccu RST_BUS_OHCI3>, > + <&ccu RST_BUS_EHCI3>; > + phys = <&usb2phy 3>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + > + ohci3: usb@5311400 { > + compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; > + reg = <0x05311400 0x100>; > + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_OHCI3>, > + <&ccu CLK_USB_OHCI3>; > + resets = <&ccu RST_BUS_OHCI3>; > + phys = <&usb2phy 3>; > + phy-names = "usb"; > + status = "disabled"; > + }; > + This didn't apply cleanly due to the new HDMI nodes. I fixed it up locally. ChenYu > r_ccu: clock@7010000 { > compatible = "allwinner,sun50i-h6-r-ccu"; > reg = <0x07010000 0x400>; > -- > 2.18.0 > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout.
于 2018年11月14日 GMT+08:00 下午6:21:33, Chen-Yu Tsai <wens@csie.org> 写到: >Hi, > >On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote: >> >> Allwinner H6 has two USB2 ports, one OTG and one host-only. >> >> Add device tree nodes related to them. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> Reviewed-by: Chen-Yu Tsai <wens@csie.org> >> --- >> No changes in v4. >> >> Changes in v3: >> - Removed the wrongly introduced usb3phy node. >> - Added Chen-Yu's Review tag. >> >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81 >++++++++++++++++++++ >> 1 file changed, 81 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> index 040828d2e2c0..3d60af6cb3ae 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi >> @@ -258,6 +258,87 @@ >> status = "disabled"; >> }; >> >> + usb2otg: usb@5100000 { >> + compatible = "allwinner,sun8i-a33-musb"; > >I added an SoC-specific compatible: "allwinner,sun50i-h6-musb". > >I'm also curious as to whether the MUSB controller was tested or not, >since Allwinner now has EHCI/OHCI host pairs for host mode, and the >Pine H64 >only does host mode. USB plug-in detection relays on MUSB if it's enabled. > >> + reg = <0x05100000 0x0400>; >> + clocks = <&ccu CLK_BUS_OTG>; >> + resets = <&ccu RST_BUS_OTG>; >> + interrupts = <GIC_SPI 23 >IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "mc"; >> + phys = <&usb2phy 0>; >> + phy-names = "usb"; >> + extcon = <&usb2phy 0>; >> + status = "disabled"; >> + }; >> + >> + usb2phy: phy@5100400 { >> + compatible = "allwinner,sun50i-h6-usb-phy"; >> + reg = <0x05100400 0x14>, >> + <0x05101800 0x4>, >> + <0x05311800 0x4>; >> + reg-names = "phy_ctrl", >> + "pmu0", >> + "pmu3"; >> + clocks = <&ccu CLK_USB_PHY0>, >> + <&ccu CLK_USB_PHY3>; >> + clock-names = "usb0_phy", >> + "usb3_phy"; >> + resets = <&ccu RST_USB_PHY0>, >> + <&ccu RST_USB_PHY3>; >> + reset-names = "usb0_reset", >> + "usb3_reset"; >> + status = "disabled"; >> + #phy-cells = <1>; >> + }; >> + >> + ehci0: usb@5101000 { >> + compatible = "allwinner,sun50i-h6-ehci", >"generic-ehci"; >> + reg = <0x05101000 0x100>; >> + interrupts = <GIC_SPI 24 >IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI0>, >> + <&ccu CLK_BUS_EHCI0>, >> + <&ccu CLK_USB_OHCI0>; >> + resets = <&ccu RST_BUS_OHCI0>, >> + <&ccu RST_BUS_EHCI0>; >> + status = "disabled"; >> + }; >> + >> + ohci0: usb@5101400 { >> + compatible = "allwinner,sun50i-h6-ohci", >"generic-ohci"; >> + reg = <0x05101400 0x100>; >> + interrupts = <GIC_SPI 25 >IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI0>, >> + <&ccu CLK_USB_OHCI0>; >> + resets = <&ccu RST_BUS_OHCI0>; >> + status = "disabled"; >> + }; >> + >> + ehci3: usb@5311000 { >> + compatible = "allwinner,sun50i-h6-ehci", >"generic-ehci"; >> + reg = <0x05311000 0x100>; >> + interrupts = <GIC_SPI 28 >IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI3>, >> + <&ccu CLK_BUS_EHCI3>, >> + <&ccu CLK_USB_OHCI3>; >> + resets = <&ccu RST_BUS_OHCI3>, >> + <&ccu RST_BUS_EHCI3>; >> + phys = <&usb2phy 3>; >> + phy-names = "usb"; >> + status = "disabled"; >> + }; >> + >> + ohci3: usb@5311400 { >> + compatible = "allwinner,sun50i-h6-ohci", >"generic-ohci"; >> + reg = <0x05311400 0x100>; >> + interrupts = <GIC_SPI 29 >IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_BUS_OHCI3>, >> + <&ccu CLK_USB_OHCI3>; >> + resets = <&ccu RST_BUS_OHCI3>; >> + phys = <&usb2phy 3>; >> + phy-names = "usb"; >> + status = "disabled"; >> + }; >> + > >This didn't apply cleanly due to the new HDMI nodes. I fixed it up >locally. > >ChenYu > >> r_ccu: clock@7010000 { >> compatible = "allwinner,sun50i-h6-r-ccu"; >> reg = <0x07010000 0x400>; >> -- >> 2.18.0 >> >> -- >> You received this message because you are subscribed to the Google >Groups "linux-sunxi" group. >> To unsubscribe from this group and stop receiving emails from it, >send an email to linux-sunxi+unsubscribe@googlegroups.com. >> For more options, visit https://groups.google.com/d/optout.
On Wed, Nov 14, 2018 at 6:31 PM Icenowy Zheng <icenowy@aosc.io> wrote: > 于 2018年11月14日 GMT+08:00 下午6:21:33, Chen-Yu Tsai <wens@csie.org> 写到: > >Hi, > > > >On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote: > >> > >> Allwinner H6 has two USB2 ports, one OTG and one host-only. > >> > >> Add device tree nodes related to them. > >> > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > >> Reviewed-by: Chen-Yu Tsai <wens@csie.org> > >> --- > >> No changes in v4. > >> > >> Changes in v3: > >> - Removed the wrongly introduced usb3phy node. > >> - Added Chen-Yu's Review tag. > >> > >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81 > >++++++++++++++++++++ > >> 1 file changed, 81 insertions(+) > >> > >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > >b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > >> index 040828d2e2c0..3d60af6cb3ae 100644 > >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > >> @@ -258,6 +258,87 @@ > >> status = "disabled"; > >> }; > >> > >> + usb2otg: usb@5100000 { > >> + compatible = "allwinner,sun8i-a33-musb"; > > > >I added an SoC-specific compatible: "allwinner,sun50i-h6-musb". > > > >I'm also curious as to whether the MUSB controller was tested or not, > >since Allwinner now has EHCI/OHCI host pairs for host mode, and the > >Pine H64 > >only does host mode. > > USB plug-in detection relays on MUSB if it's enabled. That's not what I meant. Have you actually used the MUSB core in either device or host mode to know that it is compatible with the A33? And that it works correctly? IIRC ID detection is done by the PHY driver, using the GPIO lines. In host mode, since it's already directly routed to the host pair, it's the host pair that does plug-in detection. The MUSB core is completely unused. It should be quite clear if you look at the times each interrupt line fired. ChenYu > > > >> + reg = <0x05100000 0x0400>; > >> + clocks = <&ccu CLK_BUS_OTG>; > >> + resets = <&ccu RST_BUS_OTG>; > >> + interrupts = <GIC_SPI 23 > >IRQ_TYPE_LEVEL_HIGH>; > >> + interrupt-names = "mc"; > >> + phys = <&usb2phy 0>; > >> + phy-names = "usb"; > >> + extcon = <&usb2phy 0>; > >> + status = "disabled"; > >> + }; > >> + > >> + usb2phy: phy@5100400 { > >> + compatible = "allwinner,sun50i-h6-usb-phy"; > >> + reg = <0x05100400 0x14>, > >> + <0x05101800 0x4>, > >> + <0x05311800 0x4>; > >> + reg-names = "phy_ctrl", > >> + "pmu0", > >> + "pmu3"; > >> + clocks = <&ccu CLK_USB_PHY0>, > >> + <&ccu CLK_USB_PHY3>; > >> + clock-names = "usb0_phy", > >> + "usb3_phy"; > >> + resets = <&ccu RST_USB_PHY0>, > >> + <&ccu RST_USB_PHY3>; > >> + reset-names = "usb0_reset", > >> + "usb3_reset"; > >> + status = "disabled"; > >> + #phy-cells = <1>; > >> + }; > >> + > >> + ehci0: usb@5101000 { > >> + compatible = "allwinner,sun50i-h6-ehci", > >"generic-ehci"; > >> + reg = <0x05101000 0x100>; > >> + interrupts = <GIC_SPI 24 > >IRQ_TYPE_LEVEL_HIGH>; > >> + clocks = <&ccu CLK_BUS_OHCI0>, > >> + <&ccu CLK_BUS_EHCI0>, > >> + <&ccu CLK_USB_OHCI0>; > >> + resets = <&ccu RST_BUS_OHCI0>, > >> + <&ccu RST_BUS_EHCI0>; > >> + status = "disabled"; > >> + }; > >> + > >> + ohci0: usb@5101400 { > >> + compatible = "allwinner,sun50i-h6-ohci", > >"generic-ohci"; > >> + reg = <0x05101400 0x100>; > >> + interrupts = <GIC_SPI 25 > >IRQ_TYPE_LEVEL_HIGH>; > >> + clocks = <&ccu CLK_BUS_OHCI0>, > >> + <&ccu CLK_USB_OHCI0>; > >> + resets = <&ccu RST_BUS_OHCI0>; > >> + status = "disabled"; > >> + }; > >> + > >> + ehci3: usb@5311000 { > >> + compatible = "allwinner,sun50i-h6-ehci", > >"generic-ehci"; > >> + reg = <0x05311000 0x100>; > >> + interrupts = <GIC_SPI 28 > >IRQ_TYPE_LEVEL_HIGH>; > >> + clocks = <&ccu CLK_BUS_OHCI3>, > >> + <&ccu CLK_BUS_EHCI3>, > >> + <&ccu CLK_USB_OHCI3>; > >> + resets = <&ccu RST_BUS_OHCI3>, > >> + <&ccu RST_BUS_EHCI3>; > >> + phys = <&usb2phy 3>; > >> + phy-names = "usb"; > >> + status = "disabled"; > >> + }; > >> + > >> + ohci3: usb@5311400 { > >> + compatible = "allwinner,sun50i-h6-ohci", > >"generic-ohci"; > >> + reg = <0x05311400 0x100>; > >> + interrupts = <GIC_SPI 29 > >IRQ_TYPE_LEVEL_HIGH>; > >> + clocks = <&ccu CLK_BUS_OHCI3>, > >> + <&ccu CLK_USB_OHCI3>; > >> + resets = <&ccu RST_BUS_OHCI3>; > >> + phys = <&usb2phy 3>; > >> + phy-names = "usb"; > >> + status = "disabled"; > >> + }; > >> + > > > >This didn't apply cleanly due to the new HDMI nodes. I fixed it up > >locally. > > > >ChenYu > > > >> r_ccu: clock@7010000 { > >> compatible = "allwinner,sun50i-h6-r-ccu"; > >> reg = <0x07010000 0x400>; > >> -- > >> 2.18.0 > >> > >> -- > >> You received this message because you are subscribed to the Google > >Groups "linux-sunxi" group. > >> To unsubscribe from this group and stop receiving emails from it, > >send an email to linux-sunxi+unsubscribe@googlegroups.com. > >> For more options, visit https://groups.google.com/d/optout. > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout.
On Thu, Nov 15, 2018 at 10:16 AM Chen-Yu Tsai <wens@csie.org> wrote: > > On Wed, Nov 14, 2018 at 6:31 PM Icenowy Zheng <icenowy@aosc.io> wrote: > > 于 2018年11月14日 GMT+08:00 下午6:21:33, Chen-Yu Tsai <wens@csie.org> 写到: > > >Hi, > > > > > >On Thu, Oct 4, 2018 at 8:30 PM Icenowy Zheng <icenowy@aosc.io> wrote: > > >> > > >> Allwinner H6 has two USB2 ports, one OTG and one host-only. > > >> > > >> Add device tree nodes related to them. > > >> > > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > > >> Reviewed-by: Chen-Yu Tsai <wens@csie.org> > > >> --- > > >> No changes in v4. > > >> > > >> Changes in v3: > > >> - Removed the wrongly introduced usb3phy node. > > >> - Added Chen-Yu's Review tag. > > >> > > >> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 81 > > >++++++++++++++++++++ > > >> 1 file changed, 81 insertions(+) > > >> > > >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > >b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > >> index 040828d2e2c0..3d60af6cb3ae 100644 > > >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi > > >> @@ -258,6 +258,87 @@ > > >> status = "disabled"; > > >> }; > > >> > > >> + usb2otg: usb@5100000 { > > >> + compatible = "allwinner,sun8i-a33-musb"; > > > > > >I added an SoC-specific compatible: "allwinner,sun50i-h6-musb". > > > > > >I'm also curious as to whether the MUSB controller was tested or not, > > >since Allwinner now has EHCI/OHCI host pairs for host mode, and the > > >Pine H64 > > >only does host mode. > > > > USB plug-in detection relays on MUSB if it's enabled. > > That's not what I meant. Have you actually used the MUSB core in either > device or host mode to know that it is compatible with the A33? And > that it works correctly? > > IIRC ID detection is done by the PHY driver, using the GPIO lines. > In host mode, since it's already directly routed to the host pair, > it's the host pair that does plug-in detection. The MUSB core is > completely unused. It should be quite clear if you look at the times > each interrupt line fired. I forced the routing to use MUSB and it looks like it works OK. And the BSP figures for the number of endpoints looks correct. I'll push the patches out. Thanks. ChenYu
Hi, On 14/11/18 10:27 AM, Icenowy Zheng wrote: > 在 2018-10-04四的 20:28 +0800，Icenowy Zheng写道： >> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also >> controlled). >> >> Add a driver for it. >> >> The register operations in this driver is mainly extracted from the >> BSP >> USB3 driver. >> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> >> Reviewed-by: Chen-Yu Tsai <wens@csie.org> > > Kishon, I see this patch is picked to linux-next, however this patch is > not in the stage that can be picked, because for the Vbus of USB3 PHY > Rob Herring still have some problems. > > Could you remove PATCH 7 and 8 in this patchset now? I've updated my tree now. Thanks Kishon > > Thanks! > >> --- >> Changes in v4: >> - Added support for vbus-supply property. >> >> Changes in v3: >> - Dropped USB_SUPPORT dependency. >> - Added Chen-Yu's Review tag. >> >> No changes in v2, v1. >> >> drivers/phy/allwinner/Kconfig | 12 ++ >> drivers/phy/allwinner/Makefile | 1 + >> drivers/phy/allwinner/phy-sun50i-usb3.c | 239 >> ++++++++++++++++++++++++ >> 3 files changed, 252 insertions(+) >> create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c >> >> diff --git a/drivers/phy/allwinner/Kconfig >> b/drivers/phy/allwinner/Kconfig >> index cdc1e745ba47..064096e6a4e5 100644 >> --- a/drivers/phy/allwinner/Kconfig >> +++ b/drivers/phy/allwinner/Kconfig >> @@ -29,3 +29,15 @@ config PHY_SUN9I_USB >> sun9i SoCs. >> >> This driver controls each individual USB 2 host PHY. >> + >> +config PHY_SUN50I_USB3 >> + tristate "Allwinner sun50i SoC USB3 PHY driver" >> + depends on ARCH_SUNXI && HAS_IOMEM && OF >> + depends on RESET_CONTROLLER >> + select USB_COMMON >> + select GENERIC_PHY >> + help >> + Enable this to support the USB3.0-capable transceiver that is >> + part of some Allwinner sun50i SoCs. >> + >> + This driver controls each individual USB 2+3 host PHY combo. >> diff --git a/drivers/phy/allwinner/Makefile >> b/drivers/phy/allwinner/Makefile >> index 8605529c01a1..a8d01e9073c2 100644 >> --- a/drivers/phy/allwinner/Makefile >> +++ b/drivers/phy/allwinner/Makefile >> @@ -1,2 +1,3 @@ >> obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o >> obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o >> +obj-$(CONFIG_PHY_SUN50I_USB3) += phy-sun50i-usb3.o >> diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c >> b/drivers/phy/allwinner/phy-sun50i-usb3.c >> new file mode 100644 >> index 000000000000..70c299c01c3e >> --- /dev/null >> +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c >> @@ -0,0 +1,239 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * Allwinner sun50i(H6) USB 3.0 phy driver >> + * >> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> >> + * >> + * Based on phy-sun9i-usb.c, which is: >> + * >> + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org> >> + * >> + * Based on code from Allwinner BSP, which is: >> + * >> + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd. >> + */ >> + >> +#include <linux/clk.h> >> +#include <linux/err.h> >> +#include <linux/io.h> >> +#include <linux/module.h> >> +#include <linux/phy/phy.h> >> +#include <linux/usb/of.h> >> +#include <linux/platform_device.h> >> +#include <linux/regulator/consumer.h> >> +#include <linux/reset.h> >> + >> +/* Interface Status and Control Registers */ >> +#define SUNXI_ISCR 0x00 >> +#define SUNXI_PIPE_CLOCK_CONTROL 0x14 >> +#define SUNXI_PHY_TUNE_LOW 0x18 >> +#define SUNXI_PHY_TUNE_HIGH 0x1c >> +#define SUNXI_PHY_EXTERNAL_CONTROL 0x20 >> + >> +/* USB2.0 Interface Status and Control Register */ >> +#define SUNXI_ISCR_FORCE_VBUS (3 << 12) >> + >> +/* PIPE Clock Control Register */ >> +#define SUNXI_PCC_PIPE_CLK_OPEN (1 << 6) >> + >> +/* PHY External Control Register */ >> +#define SUNXI_PEC_EXTERN_VBUS (3 << 1) >> +#define SUNXI_PEC_SSC_EN (1 << 24) >> +#define SUNXI_PEC_REF_SSP_EN (1 << 26) >> + >> +/* PHY Tune High Register */ >> +#define SUNXI_TX_DEEMPH_3P5DB(n) ((n) << 19) >> +#define SUNXI_TX_DEEMPH_3P5DB_MASK GENMASK(24, 19) >> +#define SUNXI_TX_DEEMPH_6DB(n) ((n) << 13) >> +#define SUNXI_TX_DEEMPH_6GB_MASK GENMASK(18, 13) >> +#define SUNXI_TX_SWING_FULL(n) ((n) << 6) >> +#define SUNXI_TX_SWING_FULL_MASK GENMASK(12, 6) >> +#define SUNXI_LOS_BIAS(n) ((n) << 3) >> +#define SUNXI_LOS_BIAS_MASK GENMASK(5, 3) >> +#define SUNXI_TXVBOOSTLVL(n) ((n) << 0) >> +#define SUNXI_TXVBOOSTLVL_MASK GENMASK(0, 2) >> + >> +struct sun50i_usb3_phy { >> + struct phy *phy; >> + void __iomem *regs; >> + struct reset_control *reset; >> + struct clk *clk; >> + bool regulator_on; >> + struct regulator *vbus; >> +}; >> + >> +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy) >> +{ >> + u32 val; >> + >> + val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); >> + val |= SUNXI_PEC_EXTERN_VBUS; >> + val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN; >> + writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL); >> + >> + val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL); >> + val |= SUNXI_PCC_PIPE_CLK_OPEN; >> + writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL); >> + >> + val = readl(phy->regs + SUNXI_ISCR); >> + val |= SUNXI_ISCR_FORCE_VBUS; >> + writel(val, phy->regs + SUNXI_ISCR); >> + >> + /* >> + * All the magic numbers written to the PHY_TUNE_{LOW_HIGH} >> + * registers are directly taken from the BSP USB3 driver from >> + * Allwiner. >> + */ >> + writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW); >> + >> + val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH); >> + val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK | >> + SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK | >> + SUNXI_TX_DEEMPH_3P5DB_MASK); >> + val |= SUNXI_TXVBOOSTLVL(0x7); >> + val |= SUNXI_LOS_BIAS(0x7); >> + val |= SUNXI_TX_SWING_FULL(0x55); >> + val |= SUNXI_TX_DEEMPH_6DB(0x20); >> + val |= SUNXI_TX_DEEMPH_3P5DB(0x15); >> + writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH); >> +} >> + >> +static int sun50i_usb3_phy_init(struct phy *_phy) >> +{ >> + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); >> + int ret; >> + >> + ret = clk_prepare_enable(phy->clk); >> + if (ret) >> + goto err_clk; >> + >> + ret = reset_control_deassert(phy->reset); >> + if (ret) >> + goto err_reset; >> + >> + sun50i_usb3_phy_open(phy); >> + return 0; >> + >> +err_reset: >> + clk_disable_unprepare(phy->clk); >> + >> +err_clk: >> + return ret; >> +} >> + >> +static int sun50i_usb3_phy_exit(struct phy *_phy) >> +{ >> + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); >> + >> + reset_control_assert(phy->reset); >> + clk_disable_unprepare(phy->clk); >> + >> + return 0; >> +} >> + >> +static int sun50i_usb3_phy_power_on(struct phy *_phy) >> +{ >> + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); >> + int ret; >> + >> + if (!phy->vbus || phy->regulator_on) >> + return 0; >> + >> + ret = regulator_enable(phy->vbus); >> + if (ret) >> + return ret; >> + >> + phy->regulator_on = true; >> + >> + return 0; >> +} >> + >> +static int sun50i_usb3_phy_power_off(struct phy *_phy) >> +{ >> + struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy); >> + >> + if (!phy->vbus || !phy->regulator_on) >> + return 0; >> + >> + regulator_disable(phy->vbus); >> + phy->regulator_on = false; >> + >> + return 0; >> +} >> + >> +static const struct phy_ops sun50i_usb3_phy_ops = { >> + .init = sun50i_usb3_phy_init, >> + .exit = sun50i_usb3_phy_exit, >> + .power_on = sun50i_usb3_phy_power_on, >> + .power_off = sun50i_usb3_phy_power_off, >> + .owner = THIS_MODULE, >> +}; >> + >> +static int sun50i_usb3_phy_probe(struct platform_device *pdev) >> +{ >> + struct sun50i_usb3_phy *phy; >> + struct device *dev = &pdev->dev; >> + struct phy_provider *phy_provider; >> + struct resource *res; >> + >> + phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); >> + if (!phy) >> + return -ENOMEM; >> + >> + phy->clk = devm_clk_get(dev, NULL); >> + if (IS_ERR(phy->clk)) { >> + dev_err(dev, "failed to get phy clock\n"); >> + return PTR_ERR(phy->clk); >> + } >> + >> + phy->reset = devm_reset_control_get(dev, NULL); >> + if (IS_ERR(phy->reset)) { >> + dev_err(dev, "failed to get reset control\n"); >> + return PTR_ERR(phy->reset); >> + } >> + >> + phy->vbus = devm_regulator_get_optional(dev, "vbus"); >> + if (IS_ERR(phy->vbus)) { >> + if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) { >> + dev_err(dev, "Couldn't get vbus regulator... >> Deferring probe\n"); >> + return -EPROBE_DEFER; >> + } >> + >> + phy->vbus = NULL; >> + } >> + >> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); >> + phy->regs = devm_ioremap_resource(dev, res); >> + if (IS_ERR(phy->regs)) >> + return PTR_ERR(phy->regs); >> + >> + phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops); >> + if (IS_ERR(phy->phy)) { >> + dev_err(dev, "failed to create PHY\n"); >> + return PTR_ERR(phy->phy); >> + } >> + >> + phy_set_drvdata(phy->phy, phy); >> + phy_provider = devm_of_phy_provider_register(dev, >> of_phy_simple_xlate); >> + >> + return PTR_ERR_OR_ZERO(phy_provider); >> +} >> + >> +static const struct of_device_id sun50i_usb3_phy_of_match[] = { >> + { .compatible = "allwinner,sun50i-h6-usb3-phy" }, >> + { }, >> +}; >> +MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match); >> + >> +static struct platform_driver sun50i_usb3_phy_driver = { >> + .probe = sun50i_usb3_phy_probe, >> + .driver = { >> + .of_match_table = sun50i_usb3_phy_of_match, >> + .name = "sun50i-usb3-phy", >> + } >> +}; >> +module_platform_driver(sun50i_usb3_phy_driver); >> + >> +MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver"); >> +MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); >> +MODULE_LICENSE("GPL"); >