| Message ID | 20180216060503.22006-1-rnayak@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add DTS for SDM845 SoC and MTP | expand |
Hi, On Thu, Feb 15, 2018 at 10:05 PM, Rajendra Nayak <rnayak@codeaurora.org> wrote: > Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Reviewed-by: Doug Anderson <dianders@chromium.org> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++ > 3 files changed, 293 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts > create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 55ec5ee7f7e8..9319e74b8906 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb > dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb > dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb > dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb > diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > new file mode 100644 > index 000000000000..979ab49913f1 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > @@ -0,0 +1,15 @@ > +// SPDX-License-Identifier: GPL-2.0 This already has my Reviewed-by tag (and that's great), but just making it clear that I am in favor of this landing with just the GPL-2.0 license and not block waiting on the QC lawyers to hash out whether the device tree can really be dual-licensed. If lawyers come back soon then it will be easy to have a followup patch that changes this. Since (I don't think) any hobbyists have an SDM845 in their hands right now it seems unlikely to be hard to track down any authors in the meantime and make sure they're OK. If lawyers don't come back soon then it will be a good thing that we didn't block. Having this skeleton DTS file land sooner rather than later will unblock other patches to be sent out enabling other peripherals, which seems like a nice thing. :) -Doug -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Thu, Feb 15, 2018 at 10:05 PM, Rajendra Nayak <rnayak@codeaurora.org> wrote: > Add the qup uart node and geni se instance needed to > support the serial console on the MTP. > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +++++++++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 39 +++++++++++++++++++++++++++++++++ > 2 files changed, 78 insertions(+) Looks nice to me. Thanks! As in your cover letter, this patch will almost certainly need to be spun again because it's based on bindings that have review feedback. For those of you playing along at home, see <https://patchwork.kernel.org/patch/10162063/>. Thus, I'm not providing a Reviewed-by tag at the moemnt. I will still say thanks for posting this (even though it was based on old bindings) since it allowed us to make some good progress ahead of time so we'll be very close to landing when the serial patch is spun next. In my ideal world the first 3 patches of this series would land sooner rather than later and then this 4th patch would simply be re-posted on its own when the bindings get more finalized (or, even better, if the first 3 patches have landed then Karthikeyan could just glom this on to the end of his next spin of the serial driver. ;-) -Doug -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, 16 Feb 2018 11:35:02 +0530 Rajendra Nayak <rnayak@codeaurora.org> wrote: > Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Reviewed-by: Doug Anderson <dianders@chromium.org> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ > arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++ > 3 files changed, 293 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts > create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi > [...] > diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi > new file mode 100644 > index 000000000000..c46e726af621 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi > @@ -0,0 +1,277 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * SDM845 SoC device tree source > + * > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + memory@80000000 { > + device_type = "memory"; > + /* We expect the bootloader to fill in the size */ > + reg = <0 0x80000000 0 0>; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + next-level-cache = <&L2_100>; > + L2_100: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + next-level-cache = <&L2_200>; > + L2_200: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + next-level-cache = <&L2_300>; > + L2_300: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU4: cpu@400 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x400>; > + enable-method = "psci"; > + next-level-cache = <&L2_400>; > + L2_400: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU5: cpu@500 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x500>; > + enable-method = "psci"; > + next-level-cache = <&L2_500>; > + L2_500: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU6: cpu@600 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x600>; > + enable-method = "psci"; > + next-level-cache = <&L2_600>; > + L2_600: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU7: cpu@700 { > + device_type = "cpu"; > + compatible = "qcom,kryo385"; > + reg = <0x0 0x700>; > + enable-method = "psci"; > + next-level-cache = <&L2_700>; > + L2_700: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; > + }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <19200000>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <32764>; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + soc: soc { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0 0 0xffffffff>; > + compatible = "simple-bus"; > + > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + #interrupt-cells = <3>; > + interrupt-controller; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + reg = <0x17a00000 0x10000>, /* GICD */ > + <0x17a60000 0x100000>; /* GICR * 8 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + > + gic-its@17a40000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + #msi-cells = <1>; > + reg = <0x17a40000 0x20000>; > + status = "disabled"; > + }; > + }; > + > + gcc: clock-controller@100000 { > + compatible = "qcom,gcc-sdm845"; > + reg = <0x100000 0x1f0000>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + tlmm: pinctrl@3400000 { > + compatible = "qcom,sdm845-pinctrl"; > + reg = <0x03400000 0xc00000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>; Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC binding. Set it to the actual trigger value. > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + timer@17c90000 { > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + compatible = "arm,armv7-timer-mem"; > + reg = <0x17c90000 0x1000>; > + > + frame@17ca0000 { > + frame-number = <0>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x17ca0000 0x1000>, > + <0x17cb0000 0x1000>; > + }; > + > + frame@17cc0000 { > + frame-number = <1>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x17cc0000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17cd0000 { > + frame-number = <2>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x17cd0000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17ce0000 { > + frame-number = <3>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x17ce0000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17cf0000 { > + frame-number = <4>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x17cf0000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17d00000 { > + frame-number = <5>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x17d00000 0x1000>; > + status = "disabled"; > + }; > + > + frame@17d10000 { > + frame-number = <6>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x17d10000 0x1000>; > + status = "disabled"; > + }; > + }; > + > + spmi_bus: spmi@c440000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0xc440000 0x1100>, > + <0xc600000 0x2000000>, > + <0xe600000 0x100000>, > + <0xe700000 0xa0000>, > + <0xc40a000 0x26000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > + interrupt-names = "periph_irq"; > + interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; Same here. > + qcom,ee = <0>; > + qcom,channel = <0>; > + #address-cells = <2>; > + #size-cells = <0>; > + interrupt-controller; > + #interrupt-cells = <4>; > + cell-index = <0>; > + }; > + }; > +}; Thanks, M.
Hi, On Mon, Feb 19, 2018 at 8:36 AM, Marc Zyngier <marc.zyngier@arm.com> wrote: >> + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>; > > Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC > binding. Set it to the actual trigger value. > >> + interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; > > Same here. Thanks for the review Marc! Andy: If I'm reading everything correctly you're the one who would collect these patches and apply them. Is that right? Do they look OK to you in general? Would you prefer that Rajendra send out a v5 with the fixes pointed out by Marc, or would you prefer to fix them up yourself when applying? Is now a good time or would you prefer to wait? Thanks! :) -Doug -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 02/19/2018 10:06 PM, Marc Zyngier wrote: > On Fri, 16 Feb 2018 11:35:02 +0530 > Rajendra Nayak <rnayak@codeaurora.org> wrote: > >> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files >> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> Reviewed-by: Doug Anderson <dianders@chromium.org> >> --- >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ >> arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++ >> 3 files changed, 293 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts >> create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi [...] >> + >> + soc: soc { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges = <0 0 0 0xffffffff>; >> + compatible = "simple-bus"; >> + >> + intc: interrupt-controller@17a00000 { >> + compatible = "arm,gic-v3"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + #redistributor-regions = <1>; >> + redistributor-stride = <0x0 0x20000>; >> + reg = <0x17a00000 0x10000>, /* GICD */ >> + <0x17a60000 0x100000>; /* GICR * 8 */ >> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; >> + >> + gic-its@17a40000 { >> + compatible = "arm,gic-v3-its"; >> + msi-controller; >> + #msi-cells = <1>; >> + reg = <0x17a40000 0x20000>; >> + status = "disabled"; >> + }; >> + }; >> + >> + gcc: clock-controller@100000 { >> + compatible = "qcom,gcc-sdm845"; >> + reg = <0x100000 0x1f0000>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> + tlmm: pinctrl@3400000 { >> + compatible = "qcom,sdm845-pinctrl"; >> + reg = <0x03400000 0xc00000>; >> + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>; > > Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC > binding. Set it to the actual trigger value. Thanks Marc for the review. I fixed these up and did a respin.
On 02/22/2018 04:53 AM, Doug Anderson wrote: > Hi, > > On Mon, Feb 19, 2018 at 8:36 AM, Marc Zyngier <marc.zyngier@arm.com> wrote: >>> + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>; >> >> Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC >> binding. Set it to the actual trigger value. >> > >>> + interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>; >> >> Same here. > > Thanks for the review Marc! > > > Andy: If I'm reading everything correctly you're the one who would > collect these patches and apply them. Is that right? Do they look OK > to you in general? Would you prefer that Rajendra send out a v5 with > the fixes pointed out by Marc, or would you prefer to fix them up > yourself when applying? Is now a good time or would you prefer to > wait? I just fixed up to remove all instances of IRQ_TYPE_NONE and sent a v5 out. > > Thanks! :) > > -Doug > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >