| Message ID | 20171219080747.4507-1-embed3d@gmail.com |
|---|---|
| Headers | show |
| Series | arm: sunxi: IR support for A83T | expand |
Hi Philipp, On Tue, Dec 19, 2017 at 09:07:42AM +0100, Philipp Rossak wrote: > This patch updates the sunxi-ir driver to set the base clock frequency from > devicetree. > > This is necessary since there are different ir receivers on the > market, that operate with different frequencies. So this value could be > set if the attached ir receiver needs a different base clock frequency, > than the default 8 MHz. > > Signed-off-by: Philipp Rossak <embed3d@gmail.com> feel free to add Reviewed-by: Andi Shyti <andi.shyti@samsung.com> Andi -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Tue, Dec 19, 2017 at 09:07:41AM +0100, Philipp Rossak wrote: > This patch series adds support for the sunxi A83T ir module and enhances > the sunxi-ir driver. Right now the base clock frequency for the ir driver > is a hard coded define and is set to 8 MHz. > This works for the most common ir receivers. On the Sinovoip Bananapi M3 > the ir receiver needs, a 3 MHz base clock frequency to work without > problems with this driver. > > This patch series adds support for an optinal property that makes it able > to override the default base clock frequency and enables the ir interface > on the a83t and the Bananapi M3. > > changes since v2: > * reorder cir pin (alphabetical) > * fix typo in documentation > > changes since v1: > * fix typos, reword Documentation > * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement > * change dev_info() to dev_dbg() > * change naming to cir* in dts/dtsi > * Added acked Ackedi-by to related patch > * use whole memory block instead of registers needed + fix for h3/h5 > > changes since rfc: > * The property is now optinal. If the property is not available in > the dtb the driver uses the default base clock frequency. > * the driver prints out the the selected base clock frequency. > * changed devicetree property from base-clk-frequency to clock-frequency > > Regards, > Philipp > > > Philipp Rossak (6): > media: rc: update sunxi-ir driver to get base clock frequency from > devicetree > media: dt: bindings: Update binding documentation for sunxi IR > controller > arm: dts: sun8i: a83t: Add the cir pin for the A83T > arm: dts: sun8i: a83t: Add support for the cir interface > arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller > arm: dts: sun8i: h3-h8: ir register size should be the whole memory > block I can take this series (through rc-core, i.e. linux-media), but I need an maintainer Acked-by: for the sun[x8]i dts changes (all four patches). > Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ > arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++++++ > arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++ > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- > drivers/media/rc/sunxi-cir.c | 19 +++++++++++-------- > 5 files changed, 37 insertions(+), 9 deletions(-) Thanks Sean -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi, On Fri, Jan 05, 2018 at 12:02:53PM +0000, Sean Young wrote: > On Tue, Dec 19, 2017 at 09:07:41AM +0100, Philipp Rossak wrote: > > This patch series adds support for the sunxi A83T ir module and enhances > > the sunxi-ir driver. Right now the base clock frequency for the ir driver > > is a hard coded define and is set to 8 MHz. > > This works for the most common ir receivers. On the Sinovoip Bananapi M3 > > the ir receiver needs, a 3 MHz base clock frequency to work without > > problems with this driver. > > > > This patch series adds support for an optinal property that makes it able > > to override the default base clock frequency and enables the ir interface > > on the a83t and the Bananapi M3. > > > > changes since v2: > > * reorder cir pin (alphabetical) > > * fix typo in documentation > > > > changes since v1: > > * fix typos, reword Documentation > > * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement > > * change dev_info() to dev_dbg() > > * change naming to cir* in dts/dtsi > > * Added acked Ackedi-by to related patch > > * use whole memory block instead of registers needed + fix for h3/h5 > > > > changes since rfc: > > * The property is now optinal. If the property is not available in > > the dtb the driver uses the default base clock frequency. > > * the driver prints out the the selected base clock frequency. > > * changed devicetree property from base-clk-frequency to clock-frequency > > > > Regards, > > Philipp > > > > > > Philipp Rossak (6): > > media: rc: update sunxi-ir driver to get base clock frequency from > > devicetree > > media: dt: bindings: Update binding documentation for sunxi IR > > controller > > arm: dts: sun8i: a83t: Add the cir pin for the A83T > > arm: dts: sun8i: a83t: Add support for the cir interface > > arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller > > arm: dts: sun8i: h3-h8: ir register size should be the whole memory > > block > > I can take this series (through rc-core, i.e. linux-media), but I need an > maintainer Acked-by: for the sun[x8]i dts changes (all four patches). We'll merge them through our tree. We usually have a rather big number of patches around, so we'd be better off avoiding conflicts :) Philipp, can you resubmit the DTs as soon as -rc1 is out? Thanks! Maxime
On Tue, Dec 19, 2017 at 09:07:42AM +0100, Philipp Rossak wrote: > This patch updates the sunxi-ir driver to set the base clock frequency from > devicetree. > > This is necessary since there are different ir receivers on the > market, that operate with different frequencies. So this value could be > set if the attached ir receiver needs a different base clock frequency, > than the default 8 MHz. > > Signed-off-by: Philipp Rossak <embed3d@gmail.com> Acked-by: Sean Young <sean@mess.org> Sean > --- > drivers/media/rc/sunxi-cir.c | 19 +++++++++++-------- > 1 file changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c > index 97f367b446c4..f500cea228a9 100644 > --- a/drivers/media/rc/sunxi-cir.c > +++ b/drivers/media/rc/sunxi-cir.c > @@ -72,12 +72,8 @@ > /* CIR_REG register idle threshold */ > #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8))) > > -/* Required frequency for IR0 or IR1 clock in CIR mode */ > +/* Required frequency for IR0 or IR1 clock in CIR mode (default) */ > #define SUNXI_IR_BASE_CLK 8000000 > -/* Frequency after IR internal divider */ > -#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64) > -/* Sample period in ns */ > -#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK) > /* Noise threshold in samples */ > #define SUNXI_IR_RXNOISE 1 > /* Idle Threshold in samples */ > @@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) > /* for each bit in fifo */ > dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); > rawir.pulse = (dt & 0x80) != 0; > - rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE; > + rawir.duration = ((dt & 0x7f) + 1) * > + ir->rc->rx_resolution; > ir_raw_event_store_with_filter(ir->rc, &rawir); > } > } > @@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev) > struct device_node *dn = dev->of_node; > struct resource *res; > struct sunxi_ir *ir; > + u32 b_clk_freq = SUNXI_IR_BASE_CLK; > > ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL); > if (!ir) > @@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev) > return PTR_ERR(ir->clk); > } > > + /* Base clock frequency (optional) */ > + of_property_read_u32(dn, "clock-frequency", &b_clk_freq); > + > /* Reset (optional) */ > ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL); > if (IS_ERR(ir->rst)) > @@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev) > if (ret) > return ret; > > - ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK); > + ret = clk_set_rate(ir->clk, b_clk_freq); > if (ret) { > dev_err(dev, "set ir base clock failed!\n"); > goto exit_reset_assert; > } > + dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq); > > if (clk_prepare_enable(ir->apb_clk)) { > dev_err(dev, "try to enable apb_ir_clk failed\n"); > @@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev) > ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY; > ir->rc->dev.parent = dev; > ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; > - ir->rc->rx_resolution = SUNXI_IR_SAMPLE; > + /* Frequency after IR internal divider with sample period in ns */ > + ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64)); > ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT); > ir->rc->driver_name = SUNXI_IR_DEV; > > -- > 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 05.01.2018 15:59, Maxime Ripard wrote: > Hi, > > On Fri, Jan 05, 2018 at 12:02:53PM +0000, Sean Young wrote: >> On Tue, Dec 19, 2017 at 09:07:41AM +0100, Philipp Rossak wrote: >>> This patch series adds support for the sunxi A83T ir module and enhances >>> the sunxi-ir driver. Right now the base clock frequency for the ir driver >>> is a hard coded define and is set to 8 MHz. >>> This works for the most common ir receivers. On the Sinovoip Bananapi M3 >>> the ir receiver needs, a 3 MHz base clock frequency to work without >>> problems with this driver. >>> >>> This patch series adds support for an optinal property that makes it able >>> to override the default base clock frequency and enables the ir interface >>> on the a83t and the Bananapi M3. >>> >>> changes since v2: >>> * reorder cir pin (alphabetical) >>> * fix typo in documentation >>> >>> changes since v1: >>> * fix typos, reword Documentation >>> * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement >>> * change dev_info() to dev_dbg() >>> * change naming to cir* in dts/dtsi >>> * Added acked Ackedi-by to related patch >>> * use whole memory block instead of registers needed + fix for h3/h5 >>> >>> changes since rfc: >>> * The property is now optinal. If the property is not available in >>> the dtb the driver uses the default base clock frequency. >>> * the driver prints out the the selected base clock frequency. >>> * changed devicetree property from base-clk-frequency to clock-frequency >>> >>> Regards, >>> Philipp >>> >>> >>> Philipp Rossak (6): >>> media: rc: update sunxi-ir driver to get base clock frequency from >>> devicetree >>> media: dt: bindings: Update binding documentation for sunxi IR >>> controller >>> arm: dts: sun8i: a83t: Add the cir pin for the A83T >>> arm: dts: sun8i: a83t: Add support for the cir interface >>> arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller >>> arm: dts: sun8i: h3-h8: ir register size should be the whole memory >>> block >> >> I can take this series (through rc-core, i.e. linux-media), but I need an >> maintainer Acked-by: for the sun[x8]i dts changes (all four patches). > > We'll merge them through our tree. We usually have a rather big number > of patches around, so we'd be better off avoiding conflicts :) > > Philipp, can you resubmit the DTs as soon as -rc1 is out? > > Thanks! > Maxime > Yes, I can do this! Regards, Philipp -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver. This patch series adds support for an optinal property that makes it able to override the default base clock frequency and enables the ir interface on the a83t and the Bananapi M3. changes since v2: * reorder cir pin (alphabetical) * fix typo in documentation changes since v1: * fix typos, reword Documentation * initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement * change dev_info() to dev_dbg() * change naming to cir* in dts/dtsi * Added acked Ackedi-by to related patch * use whole memory block instead of registers needed + fix for h3/h5 changes since rfc: * The property is now optinal. If the property is not available in the dtb the driver uses the default base clock frequency. * the driver prints out the the selected base clock frequency. * changed devicetree property from base-clk-frequency to clock-frequency Regards, Philipp Philipp Rossak (6): media: rc: update sunxi-ir driver to get base clock frequency from devicetree media: dt: bindings: Update binding documentation for sunxi IR controller arm: dts: sun8i: a83t: Add the cir pin for the A83T arm: dts: sun8i: a83t: Add support for the cir interface arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller arm: dts: sun8i: h3-h8: ir register size should be the whole memory block Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++++++ arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +- drivers/media/rc/sunxi-cir.c | 19 +++++++++++-------- 5 files changed, 37 insertions(+), 9 deletions(-)