From patchwork Tue Oct 31 08:19:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 832280 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="AkNs/FFf"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yR47W3ywNz9sRn for ; Tue, 31 Oct 2017 19:21:27 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752760AbdJaIVZ (ORCPT ); Tue, 31 Oct 2017 04:21:25 -0400 Received: from mail-wm0-f44.google.com ([74.125.82.44]:53837 "EHLO mail-wm0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752466AbdJaIVX (ORCPT ); Tue, 31 Oct 2017 04:21:23 -0400 Received: by mail-wm0-f44.google.com with SMTP id r196so21259330wmf.2; Tue, 31 Oct 2017 01:21:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=E1RLI39rQySV3yQwpNBGFzcTjFaiHJ8iTJ8UsfDONfg=; b=AkNs/FFfgho4k8WWgy48glTi6824EsXmxF4Tu+hkdy56Daj4iDzHiH10lcgMnC/lJZ pUkkHhjksqP5hIvQOPPdcWijM3UlCdSWIVZPvNABbcol674Cg07tw1IBBbF886ApPqhV wZyk1P2MCB4IZdTo63xvhbY7Gao9WNcfFYfKlxHPfQQbZ5L+2hdaL5ubGuhoeHZrS7tI Fxnjvk9+8hhiiBdyX9anvziFNIXUCTgSiodtlxwRwnEu993wEVLXfF+603x/xs8dnaLJ ZGFLr6MI+pO1jZjZmbBTb6dbNPYJKFqhF2fkS2TpoQC7eGJw8jr1E+LZwjgtpL/PQGv5 A8AQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=E1RLI39rQySV3yQwpNBGFzcTjFaiHJ8iTJ8UsfDONfg=; b=Ht2N5xBT61ZijmmRJpXcsHaK9oWYmzMZjtQg6kSogvqGOOLCX1OrwxzYQGvxCu8pQz 8DWLcCpPXIKcijJMNlqB+3aZAAmLJDDCd2edH7X5UmfTqfrtHo3Un72GPD10GcFnLdkt hHoD+DrwWo6PkjlMAJX3vY1nlalN/qqu8JT1raxhVTTWxUziznTikcUKDNDOPLJX05xL KdAiwUd9W+d5s6wxnYNXwXUNRSLoFN+RSOMqepq5RJ+OjI3iZF7KeSlp5pKAFH4lqicb U8ikPlGgn8IWGVmweyBXgm39lizlqoN1VFIWmfX7+jp0b27dhXL0juGh5ORFgPpGmqks HonA== X-Gm-Message-State: AMCzsaXmK2uwP6hR+ZiukarHG/jkrl31OSc+wdgyhqkfP8GG+EKrbXgL 74o0b9NCj59AobLoqO9SY90= X-Google-Smtp-Source: ABhQp+TIqo+6R7NoZqYD1+FgHLASVgUa1V8NxtmKY5BXAszhMILwQWzMnnaxtbtC2dZ2BkKK/WVPwA== X-Received: by 10.28.230.216 with SMTP id e85mr1298404wmi.86.1509438081602; Tue, 31 Oct 2017 01:21:21 -0700 (PDT) Received: from Red.local (LFbn-MAR-1-580-96.w90-118.abo.wanadoo.fr. [90.118.159.96]) by smtp.googlemail.com with ESMTPSA id d18sm796423wra.50.2017.10.31.01.21.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 31 Oct 2017 01:21:21 -0700 (PDT) From: Corentin Labbe To: robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will.deacon@arm.com Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Corentin Labbe Subject: [PATCH v10 0/8] net: stmmac: dwmac-sun8i: Handle integrated PHY Date: Tue, 31 Oct 2017 09:19:07 +0100 Message-Id: <20171031081915.18960-1-clabbe.montjoie@gmail.com> X-Mailer: git-send-email 2.13.6 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello The current way to find if the PHY is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to handle this problem via a mdio-mux. The first try was to create a new MDIO mux "mdio-mux-syscon". mdio-mux-syscon working the same way than mdio-mux-mmioreg with the exception that the register is used via syscon/regmap. But this solution does not work for two reason: - changing the MDIO selection need the reset of MAC which cannot be done by the mdio-mux-syscon driver - There were driver loading order problem: - mdio-mux-syscon needing that stmmac register the parent MDIO - stmmac needing that child MDIO was registered just after registering parent MDIO So we cannot use any external MDIO-mux. The final solution was to represent the mdio-mux in MAC node and let the MAC handle all things. Since DT bits was reverted in 4.13, this patch series include the revert of the revert. I have let patch splited for easy review. (for seeing what's new) But the final serie could have some patch squashed if someone want. Like squashing patch and 1 and 2 (documentation) All patchs should go via the sunxi tree Regards Changes since v9: - added a line before mdio-parent-bus - removed mdio-mux compatible from doc - fix arm prefix uppercase - splitted changes between A64 and H5 - removed already merge patchs for net Changes since v8: - added reference to mdio-mux.txt in documentation - removed compatible mdio-mux - added mdio-parent-bus Changes since v7: - moved mdio-mux ouf of mdio as asked by Andrew Lunn - reordered patchs order Changes since v6: - renamed external mdio to "external_mdio" - added compatible to mdio-mux and internal-mdio - removed usage of phy-is-integrated - renamed do_not_scan to compatible_muxes (patch 10) - patch 8 9 of v6 are squashed Changes since v5: - reordered patch 1 and 2 - mdio-mux node is now a mdio's child - added patch 11 for removing unnecessary scan of mdio-mux Changes since v4: - Update documentation for new bindings - Added 4 patchs for bring back reverted stuff of 4.13 - dwmac-sun8i now handle mdio-mux - MDIO use now compatible = "snps,dwmac-mdio"; Changes since v3: - Added a patch for handling fixed-link - Updated documentation Changes since v2: - Add a MDIO mux for creating distinction between integrated and external MDIO. - phy-is-integrated is not set in dtsi. Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (8): dt-bindings: net: Restore sun8i dwmac binding dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY arm: dts: sunxi: h3/h5: Restore EMAC changes ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac ARM: dts: sunxi: Restore EMAC changes (boards) arm64: dts: allwinner: A64: Restore EMAC changes arm64: dts: allwinner: H5: Restore EMAC changes arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio .../devicetree/bindings/net/dwmac-sun8i.txt | 207 +++++++++++++++++++++ arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 + arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 ++ arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19 ++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 49 +++++ .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 ++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 ++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 ++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 ++ .../dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 ++ 20 files changed, 513 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt