From patchwork Mon Jan 7 10:07:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 1021246 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43YB1G3RsLz9sMp for ; Mon, 7 Jan 2019 21:08:34 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726820AbfAGKI2 (ORCPT ); Mon, 7 Jan 2019 05:08:28 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:42940 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726714AbfAGKIT (ORCPT ); Mon, 7 Jan 2019 05:08:19 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x07A3hjY001107; Mon, 7 Jan 2019 11:07:58 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2ptvjffee0-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 07 Jan 2019 11:07:58 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0A9E43A; Mon, 7 Jan 2019 10:07:56 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id CA75D2A00; Mon, 7 Jan 2019 10:07:56 +0000 (GMT) Received: from localhost (10.75.127.47) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 7 Jan 2019 11:07:56 +0100 From: Fabrice Gasnier To: , CC: , , , , , , , , , Subject: [RESEND PATCH v2 0/3] mfd: syscon: Add optional clock support needed on stm32 Date: Mon, 7 Jan 2019 11:07:42 +0100 Message-ID: <1546855665-26218-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG8NODE2.st.com (10.75.127.23) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-07_04:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org STM32 syscfg registers are accessed using syscon. It needs syscfg clock to be enabled while accessing registers. This adds support for optional clock on syscon, and the relevant clock in stm32mp157 device tree. Changes in v2: - move clocks to specific bindings using syscon as per Rob's comment Fabrice Gasnier (3): dt-bindings: stm32: syscon: add clock support mfd: syscon: Add optional clock support ARM: dts: stm32: Add clock on stm32mp157c syscfg .../devicetree/bindings/arm/stm32/stm32-syscon.txt | 2 ++ arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/mfd/syscon.c | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+)