From patchwork Thu Dec 13 23:14:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1013202 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="ZpOn5i61"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43G8f66Ysnz9s4s for ; Fri, 14 Dec 2018 10:14:54 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727042AbeLMXOx (ORCPT ); Thu, 13 Dec 2018 18:14:53 -0500 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:15458 "EHLO esa2.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726236AbeLMXOw (ORCPT ); Thu, 13 Dec 2018 18:14:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1544742895; x=1576278895; h=from:to:cc:subject:date:message-id; bh=RTsWalh1XbKdBNzRQGYMWqHt94ahyZseETm1+e2I45A=; b=ZpOn5i613aYEEnfPPoqVOgzaWAx5Gc3F9JLfsxByXGF9thcEkBEV2/aX I/VHghHGv0Bp7kwnig3RWJK+GmkLGYLGk5j+7a+DHaLOuEsWXPxReObjt Fkuue2OWYm5v4/QVhSNJMIchpYAnl2+JS04XRzha3MMm25+/g0ITPj49A FxETibxvWy8qqoEvbYz8Wpcuxj6BBSZtNIW709hKq2HxXQOgS0EswfIa8 5tVb0/8v8+azOkY+fSn/S5TkydzQFuSsB/sZ7Y33VjhhDC4kQwMvBQPQ5 YOsxq2illStOztNV3AASFcVi38nss7jpLXcl2rnnC1BAl9J/t1ELhXTGi w==; X-IronPort-AV: E=Sophos;i="5.56,350,1539619200"; d="scan'208";a="194445532" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 14 Dec 2018 07:14:54 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 13 Dec 2018 14:57:20 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 13 Dec 2018 15:14:53 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Daniel Lezcano , devicetree@vger.kernel.org, Dmitriy Cherkasov , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Rob Herring , Thomas Gleixner , Anup Patel , Damien Le Moal , Christoph Hellwig Subject: [PATCH v2 0/4] Timer code cleanup. Date: Thu, 13 Dec 2018 15:14:25 -0800 Message-Id: <1544742869-19980-1-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch series provides an assorted timer cleanups in RISC-V. Changes from v1->v2: 1. Updated commit text in 1/4. 2. Added a timebase check for each cpu. 3. Added a warning for invalid hartid 4/4. Atish Patra (3): RISC-V: Support per-hart timebase-frequency RISC-V: Remove per cpu clocksource RISC-V: Fix non-smp kernel boot on SMP systems Palmer Dabbelt (1): dt-bindings: Correct RISC-V's timebase-frequency Documentation/devicetree/bindings/riscv/cpus.txt | 4 +- arch/riscv/kernel/time.c | 9 +---- drivers/clocksource/riscv_timer.c | 51 +++++++++++++++++++++--- 3 files changed, 49 insertions(+), 15 deletions(-) --- 2.7.4