From patchwork Mon Dec 3 20:57:27 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1007212 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="TMT8KRpH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 437y4P087yz9s8r for ; Tue, 4 Dec 2018 07:57:40 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725958AbeLCU5j (ORCPT ); Mon, 3 Dec 2018 15:57:39 -0500 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:19087 "EHLO esa3.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725951AbeLCU5j (ORCPT ); Mon, 3 Dec 2018 15:57:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1543870659; x=1575406659; h=from:to:cc:subject:date:message-id; bh=XsUIGNmzENIAYjpU3aKCVQO+zkCeeIwT6CKwkdo1OmM=; b=TMT8KRpHIakGMOYNEMqdrIkYYbj8kAjC6KLinQQiBWZbv+9Rd9OnTrLw cc0n5TqZeIdPp0vmZwwJ9VXtb9kySgVcuQzoyw8M0q2UIfe4CLdKsmxK7 4QrYy5dMmKzM6TEnVCX+YapPjwOw4IXbhG3nN8DqFtR+eND9mZZQzmRNb 2cmAafxvY2zqeDPw1EdD24epRNymH/Kuseye0tJ0Oe2xjsJIgj6T9RBsN CSxvZnWavxadzF82kyWJ9b2qNBoEaR3WOxMqIuMs8xPX6oxO/Dz+QHtft vIYGnJGE6y1unag8PPk4orOVBJ054ZZDSaMzSUYbnskR0BJ7/NtpVqlqi g==; X-IronPort-AV: E=Sophos;i="5.56,311,1539619200"; d="scan'208";a="100519854" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 04 Dec 2018 04:57:39 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 03 Dec 2018 12:39:54 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 03 Dec 2018 12:57:39 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Daniel Lezcano , devicetree@vger.kernel.org, Dmitriy Cherkasov , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Rob Herring , Thomas Gleixner , Anup Patel , Damien Le Moal Subject: [PATCH 0/4] Timer code cleanup. Date: Mon, 3 Dec 2018 12:57:27 -0800 Message-Id: <1543870651-16669-1-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch series provides an assorted timer cleanups in RISC-V. Atish Patra (3): RISC-V: Support per-hart timebase-frequency RISC-V: Remove per cpu clocksource RISC-V: Fix non-smp kernel boot on SMP systems Palmer Dabbelt (1): dt-bindings: Correct RISC-V's timebase-frequency Documentation/devicetree/bindings/riscv/cpus.txt | 4 ++- arch/riscv/kernel/time.c | 9 +----- drivers/clocksource/riscv_timer.c | 39 ++++++++++++++++++++---- 3 files changed, 37 insertions(+), 15 deletions(-) --- 2.7.4