From patchwork Thu Nov 29 23:28:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1005734 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="oTqTKDli"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 435YcF39Bqz9s9m for ; Fri, 30 Nov 2018 10:28:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726446AbeK3Kfk (ORCPT ); Fri, 30 Nov 2018 05:35:40 -0500 Received: from esa5.hgst.iphmx.com ([216.71.153.144]:50484 "EHLO esa5.hgst.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726393AbeK3Kfk (ORCPT ); Fri, 30 Nov 2018 05:35:40 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1543534107; x=1575070107; h=from:to:cc:subject:date:message-id; bh=L7Qnx+G1U15UoezilU3DKAcIr1VLVm+CQnW9+MoRsKs=; b=oTqTKDli1HZWr14a4gdRslqdsLY6gE2Ccnt1xO+D/28GAfOsRmca6iyt iW489Auj48ALeMXXiRvtQFKPpGHgPG8Gs0jXj/7j40LrbV+oIpfhHtxJi ilBPav86jOr3c8FjNNb0mCEzzhnegSt9DE96nDZmbA8HMrWvcoZqqeaHA CLtx1lIvFlTcNEp7h0MAu+DQ5tJubWSSaubo9LyEX9tA1kN+/F6Ir1pud PT/+8/4VDTqWaQVi67gcY9VzVdtssFExDUwsEtL3VCZegkzfdIUvktv7P ceIl9P2uomkoqPwDCGTDWMYXFTWO1z97yMXR9BybLjrWaS4Szo+F2pzHm Q==; X-IronPort-AV: E=Sophos;i="5.56,296,1539619200"; d="scan'208";a="96644301" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 30 Nov 2018 07:28:26 +0800 Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP; 29 Nov 2018 15:11:23 -0800 Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 29 Nov 2018 15:28:26 -0800 From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Ard Biesheuvel , Catalin Marinas , devicetree@vger.kernel.org, Dmitriy Cherkasov , Greg Kroah-Hartman , Ingo Molnar , Jeremy Linton , Juri Lelli , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-riscv@lists.infradead.org, Mark Rutland , Morten Rasmussen , Palmer Dabbelt , "Peter Zijlstra (Intel)" , "Rafael J. Wysocki" , Rob Herring , Sudeep Holla , Thomas Gleixner , Will Deacon Subject: [RFT PATCH v1 0/4] Unify CPU topology across ARM64 & RISC-V Date: Thu, 29 Nov 2018 15:28:16 -0800 Message-Id: <1543534100-3654-1-git-send-email-atish.patra@wdc.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The cpu-map DT entry in ARM64 can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent it's own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [1]. arch_topology seems to be a perfect place to move the common code. I have not introduced any functional changes in the moved code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. The patches have been tested for RISC-V and compile tested for ARM64 & x86. The socket change[2] is also now part of this series. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 QEMU changes for RISC-V topology are available at https://github.com/atishp04/riscv-qemu/tree/cpu_topo Apologies for the previous patch series with incorrect title and was sent only to kernel mailing list due to a bug in my config. Please ignore that. Atish Patra (3): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. RISC-V: Parse cpu topology during boot. Sudeep Holla (1): Documentation: DT: arm: add support for sockets defining package boundaries .../{arm/topology.txt => cpu/cpu-topology.txt} | 133 +++++++-- arch/arm64/include/asm/topology.h | 22 -- arch/arm64/kernel/topology.c | 303 +-------------------- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 + drivers/base/arch_topology.c | 294 ++++++++++++++++++++ include/linux/arch_topology.h | 26 ++ include/linux/topology.h | 1 + 8 files changed, 435 insertions(+), 348 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (66%) Acked-by:Sudeep Holla Tested-by: Jeffrey Hugo --- 2.7.4