From patchwork Tue Nov 27 16:48:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 1003925 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4348rL1zCdz9s3C for ; Wed, 28 Nov 2018 03:49:06 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726409AbeK1DrT (ORCPT ); Tue, 27 Nov 2018 22:47:19 -0500 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:64607 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726729AbeK1DrS (ORCPT ); Tue, 27 Nov 2018 22:47:18 -0500 Received: from pps.filterd (m0046037.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id wARGdOjs008239; Tue, 27 Nov 2018 17:48:26 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2nxw9x1d12-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 27 Nov 2018 17:48:26 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 20FB6348; Tue, 27 Nov 2018 17:47:57 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node3.st.com [10.75.127.15]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AB92F5330; Tue, 27 Nov 2018 16:48:25 +0000 (GMT) Received: from localhost (10.75.127.46) by SFHDAG5NODE3.st.com (10.75.127.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 27 Nov 2018 17:48:25 +0100 From: Fabrice Gasnier To: , , CC: , , , , , , , , Subject: [PATCH 0/3] mfd: syscon: Add optional clock support needed on stm32 Date: Tue, 27 Nov 2018 17:48:14 +0100 Message-ID: <1543337297-21873-1-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 X-Originating-IP: [10.75.127.46] X-ClientProxiedBy: SFHDAG1NODE1.st.com (10.75.127.1) To SFHDAG5NODE3.st.com (10.75.127.15) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-11-27_14:, , signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org STM32 syscfg registers are accessed using syscon. It needs syscfg clock to be enabled while accessing registers. This adds support for optional clock on syscon, and the relevant clock in stm32mp157 device tree. Fabrice Gasnier (3): dt-bindings: mfd: syscon: Add optional clock support mfd: syscon: Add optional clock support ARM: dts: stm32: Add clock on stm32mp157c syscfg Documentation/devicetree/bindings/mfd/syscon.txt | 1 + arch/arm/boot/dts/stm32mp157c.dtsi | 1 + drivers/mfd/syscon.c | 19 +++++++++++++++++++ 3 files changed, 21 insertions(+)