From patchwork Fri Apr 27 18:37:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thor Thayer X-Patchwork-Id: 905904 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40XjKH1SXnz9s1P for ; Sat, 28 Apr 2018 04:34:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757961AbeD0Se5 (ORCPT ); Fri, 27 Apr 2018 14:34:57 -0400 Received: from mga12.intel.com ([192.55.52.136]:62229 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757562AbeD0Se5 (ORCPT ); Fri, 27 Apr 2018 14:34:57 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 27 Apr 2018 11:34:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,336,1520924400"; d="scan'208";a="49695971" Received: from tthayer-hp-z620-workstation.an.intel.com ([10.122.105.144]) by fmsmga004.fm.intel.com with ESMTP; 27 Apr 2018 11:34:56 -0700 From: thor.thayer@linux.intel.com To: bp@alien8.de, mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: thor.thayer@linux.intel.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Subject: [PATCHv2 0/3] Add SDRAM ECC support for Stratix10 Date: Fri, 27 Apr 2018 13:37:15 -0500 Message-Id: <1524854238-19394-1-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thor Thayer The Intel Stratix10 platform is an ARM64 but still has many register definitions that are similar to the Arria10. One significant difference is the Stratix10 Secure Monitor handles registers that may be shared by guest OSes at a different exception level. Register access is through an ARM SMC call. Currently, SMC handling is implemented in Stratix10 U-Boot. Thor Thayer (3): Documentation: dt: socfpga: Add Stratix10 ECC Manager binding edac: altera: Add support for Stratix10 SDRAM EDAC arm64: dts: stratix10: add sdram ecc .../bindings/arm/altera/socfpga-eccmgr.txt | 35 ++ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 + drivers/edac/Kconfig | 2 +- drivers/edac/altera_edac.c | 455 ++++++++++++++++++++- drivers/edac/altera_edac.h | 126 +++++- 5 files changed, 602 insertions(+), 28 deletions(-) Acked-by: Dinh Nguyen