From patchwork Tue Apr 24 18:35:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thor Thayer X-Patchwork-Id: 903778 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40VsR51rpVz9s06 for ; Wed, 25 Apr 2018 04:33:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751740AbeDXSdf (ORCPT ); Tue, 24 Apr 2018 14:33:35 -0400 Received: from mga09.intel.com ([134.134.136.24]:38086 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750757AbeDXSdf (ORCPT ); Tue, 24 Apr 2018 14:33:35 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Apr 2018 11:33:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,324,1520924400"; d="scan'208";a="50471588" Received: from tthayer-hp-z620-workstation.an.intel.com ([10.122.105.144]) by orsmga001.jf.intel.com with ESMTP; 24 Apr 2018 11:33:33 -0700 From: thor.thayer@linux.intel.com To: bp@alien8.de, mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dinguyen@kernel.org, catalin.marinas@arm.com, will.deacon@arm.com Cc: thor.thayer@linux.intel.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Subject: [PATCH 0/3] Add SDRAM ECC support for Stratix10 Date: Tue, 24 Apr 2018 13:35:56 -0500 Message-Id: <1524594959-5259-1-git-send-email-thor.thayer@linux.intel.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Thor Thayer The Intel Stratix10 platform is an ARM64 but still has many register definitions that are similar to the Arria10. One significant difference is the Stratix10 hypervisor which requires handling registers that may be shared by guest OSes at a different exception level. Register access is through an ARM SMC call. Currently, SMC handling is implemented in U-Boot. Thor Thayer (3): Documentation: dt: socfpga: Add Stratix10 ECC Manager binding edac: altera: Add support for Stratix10 SDRAM EDAC arm64: dts: stratix10: add sdram ecc .../bindings/arm/altera/socfpga-eccmgr.txt | 47 +++ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 17 + drivers/edac/Kconfig | 2 +- drivers/edac/altera_edac.c | 459 +++++++++++++++++++++ drivers/edac/altera_edac.h | 114 +++++ 5 files changed, 638 insertions(+), 1 deletion(-)