diff mbox series

[RFC,01/12] arch: add hexagon architecture support

Message ID 20241025140714.2395033-2-bcain@quicinc.com
State New
Headers show
Series add hexagon architecture | expand

Commit Message

Brian Cain Oct. 25, 2024, 2:07 p.m. UTC 
Signed-off-by: Brian Cain <bcain@quicinc.com>
---
 arch/Config.in         | 10 +++++++
 arch/Config.in.hexagon | 63 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 arch/Config.in.hexagon
diff mbox series

Patch

diff --git a/arch/Config.in b/arch/Config.in
index e57f4b2baa..fe863e50a7 100644
--- a/arch/Config.in
+++ b/arch/Config.in
@@ -254,6 +254,12 @@  config BR2_xtensa
 	  http://en.wikipedia.org/wiki/Xtensa
 	  http://www.tensilica.com/
 
+config BR2_hexagon
+	bool "Hexagon"
+	select BR2_USE_MMU
+	help
+	  Hexagon is a Qualcomm DSP processor.
+
 endchoice
 
 # For some architectures or specific cores, our internal toolchain
@@ -429,6 +435,10 @@  if BR2_xtensa
 source "arch/Config.in.xtensa"
 endif
 
+if BR2_hexagon
+source "arch/Config.in.hexagon"
+endif
+
 # Set up target binary format
 choice
 	prompt "Target Binary Format"
diff --git a/arch/Config.in.hexagon b/arch/Config.in.hexagon
new file mode 100644
index 0000000000..9a7cb62278
--- /dev/null
+++ b/arch/Config.in.hexagon
@@ -0,0 +1,63 @@ 
+# hexagon cpu features
+config BR2_HEXAGON_CPU_HAS_HVX
+	bool
+
+choice
+	prompt "Target Architecture Variant"
+	default BR2_HEXAGON_v65
+	help
+	  Specific CPU variant to use
+
+config BR2_HEXAGON_v5
+	bool "v5"
+config BR2_HEXAGON_v55
+	bool "v55"
+config BR2_HEXAGON_v60
+	bool "v60"
+	select BR2_HEXAGON_CPU_HAS_HVX
+config BR2_HEXAGON_v61
+	bool "v61"
+config BR2_HEXAGON_v62
+	bool "v62"
+	select BR2_HEXAGON_CPU_HAS_HVX
+config BR2_HEXAGON_v65
+	bool "v65"
+	select BR2_HEXAGON_CPU_HAS_HVX
+config BR2_HEXAGON_v66
+	bool "v66"
+	select BR2_HEXAGON_CPU_HAS_HVX
+config BR2_HEXAGON_v68
+	bool "v68"
+	select BR2_HEXAGON_CPU_HAS_HVX
+config BR2_HEXAGON_v69
+	bool "v69"
+	select BR2_HEXAGON_CPU_HAS_HVX
+config BR2_HEXAGON_v71
+	bool "v71"
+	select BR2_HEXAGON_CPU_HAS_HVX
+config BR2_HEXAGON_v73
+	bool "v73"
+	select BR2_HEXAGON_CPU_HAS_HVX
+endchoice
+
+config BR2_ARCH
+	default "hexagon"
+
+config BR2_ENDIAN
+	default "LITTLE"
+
+config BR2_READELF_ARCH_NAME
+	default "Qualcomm Hexagon"
+
+config BR2_GCC_TARGET_CPU
+	default "hexagonv5"	if BR2_HEXAGON_v5
+	default "hexagonv55"	if BR2_HEXAGON_v55
+	default "hexagonv60"	if BR2_HEXAGON_v60
+	default "hexagonv61"	if BR2_HEXAGON_v61
+	default "hexagonv62"	if BR2_HEXAGON_v62
+	default "hexagonv65"	if BR2_HEXAGON_v65
+	default "hexagonv66"	if BR2_HEXAGON_v66
+	default "hexagonv68"	if BR2_HEXAGON_v68
+	default "hexagonv69"	if BR2_HEXAGON_v69
+	default "hexagonv71"	if BR2_HEXAGON_v71
+	default "hexagonv73"	if BR2_HEXAGON_v73