new file mode 100644
@@ -0,0 +1,58 @@
+From 0cf11f3c0478f4286adcfb09bf9137f8b00212e3 Mon Sep 17 00:00:00 2001
+From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Date: Mon, 3 Oct 2022 18:07:54 +0200
+Subject: [PATCH] riscv: Fix build against binutils 2.38
+
+The following description is copied from the equivalent patch for the
+Linux Kernel proposed by Aurelien Jarno:
+
+>From version 2.38, binutils default to ISA spec version 20191213. This
+means that the csr read/write (csrr*/csrw*) instructions and fence.i
+instruction has separated from the `I` extension, become two standalone
+extensions: Zicsr and Zifencei. As the kernel uses those instruction,
+this causes the following build failure:
+
+arch/riscv/cpu/mtrap.S: Assembler messages:
+arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause'
+arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc'
+arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval'
+arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0'
+
+Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
+Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
+Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Christian Stewart <christian@paral.in>
+Reviewed-by: Rick Chen <rick@andestech.com>
+(cherry picked from commit 1dde977518f13824b847e23275001191139bc384)
+Upstream: https://gitlab.com/u-boot/u-boot/-/commit/1dde977518f13824b847e23275001191139bc384
+Signed-off-by: Romain Naour <romain.naour@gmail.com>
+---
+ arch/riscv/Makefile | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
+index 0b80eb8d864..53d1194ffb6 100644
+--- a/arch/riscv/Makefile
++++ b/arch/riscv/Makefile
+@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
+ CMODEL = medany
+ endif
+
+-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
++RISCV_MARCH = $(ARCH_BASE)$(ARCH_A)$(ARCH_C)
++
++# Newer binutils versions default to ISA spec version 20191213 which moves some
++# instructions from the I extension to the Zicsr and Zifencei extensions.
++toolchain-need-zicsr-zifencei := $(call cc-option-yn, -mabi=$(ABI) -march=$(RISCV_MARCH)_zicsr_zifencei)
++ifeq ($(toolchain-need-zicsr-zifencei),y)
++ RISCV_MARCH := $(RISCV_MARCH)_zicsr_zifencei
++endif
++
++ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
+ -mcmodel=$(CMODEL)
+
+ PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
+--
+2.41.0
+
@@ -17,6 +17,7 @@ BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_19=y
BR2_BINFMT_FLAT=y
BR2_BINFMT_FLAT_ONE=y
# BR2_TARGET_ENABLE_ROOT_LOGIN is not set
+BR2_GLOBAL_PATCH_DIR="board/canaan/k210-soc/patches"
# Kernel
BR2_LINUX_KERNEL=y
@@ -17,6 +17,7 @@ BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_19=y
BR2_BINFMT_FLAT=y
BR2_BINFMT_FLAT_ONE=y
# BR2_TARGET_ENABLE_ROOT_LOGIN is not set
+BR2_GLOBAL_PATCH_DIR="board/canaan/k210-soc/patches"
# Kernel
BR2_LINUX_KERNEL=y
Backport an upstream patch fixing the build with binutils >= 2.38 for riscv's for Zicsr and Zifencei. Fixes: https://gitlab.com/buildroot.org/buildroot/-/jobs/4839060608 https://gitlab.com/buildroot.org/buildroot/-/jobs/4839060605 Signed-off-by: Romain Naour <romain.naour@gmail.com> --- ...iscv-Fix-build-against-binutils-2.38.patch | 58 +++++++++++++++++++ configs/sipeed_maix_bit_sdcard_defconfig | 1 + configs/sipeed_maix_dock_sdcard_defconfig | 1 + 3 files changed, 60 insertions(+) create mode 100644 board/canaan/k210-soc/patches/uboot/0001-riscv-Fix-build-against-binutils-2.38.patch