From patchwork Sun Oct 21 13:06:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Corbin X-Patchwork-Id: 987306 Return-Path: X-Original-To: incoming-buildroot@patchwork.ozlabs.org Delivered-To: patchwork-incoming-buildroot@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=busybox.net (client-ip=140.211.166.137; helo=fraxinus.osuosl.org; envelope-from=buildroot-bounces@busybox.net; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=embecosm.com header.i=@embecosm.com header.b="cyuZHoFm"; dkim-atps=neutral Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42dKgf6mzvz9sj4 for ; Mon, 22 Oct 2018 00:07:26 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id 700C98715C; Sun, 21 Oct 2018 13:07:24 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eEgfgdYKFC1m; Sun, 21 Oct 2018 13:07:22 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by fraxinus.osuosl.org (Postfix) with ESMTP id 5EDBE8714A; Sun, 21 Oct 2018 13:07:22 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133]) by ash.osuosl.org (Postfix) with ESMTP id 9D2641BF4E3 for ; Sun, 21 Oct 2018 13:07:21 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by hemlock.osuosl.org (Postfix) with ESMTP id 9AB658874B for ; Sun, 21 Oct 2018 13:07:21 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from hemlock.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id lI3glrR3VoPf for ; Sun, 21 Oct 2018 13:07:20 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by hemlock.osuosl.org (Postfix) with ESMTPS id 0837A87D0B for ; Sun, 21 Oct 2018 13:07:20 +0000 (UTC) Received: by mail-wm1-f65.google.com with SMTP id z204-v6so7685258wmc.5 for ; Sun, 21 Oct 2018 06:07:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=from:to:cc:subject:date:message-id; bh=nsf/Z+F8sHraZEQcL+5H0iJBu9zLL5wqiH5yqlFqkLM=; b=cyuZHoFmMERtOhTdtIfObVG1FU6VakZgUhWOszq2V1PRDP6v5hjA+0X1KWk9mEgfYT Ip9CMJJqkTkjfre7V7zZr2IUWd4831MRhI3vxmK30WjPsI4GvU6Qyc/OusXx8wNXu8aT dSQB3v82AV6GtKQxBTwH4z9MP7AEAFAHGG1k0SBg0ghwzMWFGfdHmUbQkGgHF1L2TtBn c5glD/4rSYKqgyFCls0Kngceryf4mr8fRZ8FFksfdjg+xP+j53hMAnMy5EZsozR8nBan t16WXToVbCBAZlVOpt2qmgXsE24NnKT25nHZemMR2/hN37ixZ1NXmtRm20e0IqnVLxF1 3A4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=nsf/Z+F8sHraZEQcL+5H0iJBu9zLL5wqiH5yqlFqkLM=; b=tbvOc8Uy6haO1dnPTdKhPO5Tq9xnBZeiN4TNlljkpbltUPsD/Ro0eYu91HLMPypCmF Xir4UJWtAScgYS9WB8wUmBj1zLY5/z3sQqHcQXcVVT8mCt/9OVEcmlT84P6QWRdO3G79 Ifsifh5+cb+QqfAkl7yVumy9/1q0wWPUkGDBCyX6YOSeibV4y0H5eEGNhz3G7XHyQ/dW F26yFmgrb3eyfz4v4PPwn3Bn3S7DQk5pnNLPRu61nSbGpAne6WzA3Wa4QbZpwX8EsG2v yC/g1yqRSf1YLegcgKfpvO6k91k4BC2BLpP02Goktvww7jX5Inz/95S1FcVkrtSYObtH IGDg== X-Gm-Message-State: ABuFfojVjyD+/g4dR57ErFuqk8offiDypoPl2P58Ky+brhzq1MyUabTh uDK+by34pUqIir/zwe5davSasOiT5o8= X-Google-Smtp-Source: ACcGV61Ga5Ruzey92qV97l2+rMklQyIiZzUpRJEWsuj0AeJ13eiM6t6VvucLeTrX/a7ab9JZD7F3fw== X-Received: by 2002:a1c:118c:: with SMTP id 134-v6mr11786934wmr.75.1540127238145; Sun, 21 Oct 2018 06:07:18 -0700 (PDT) Received: from tait.lan.virginwifi.ie ([31.185.52.13]) by smtp.gmail.com with ESMTPSA id 2-v6sm27134041wro.96.2018.10.21.06.07.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Oct 2018 06:07:17 -0700 (PDT) From: Mark Corbin To: buildroot@buildroot.org Date: Sun, 21 Oct 2018 14:06:20 +0100 Message-Id: <20181021130621.17834-1-mark.corbin@embecosm.com> X-Mailer: git-send-email 2.17.1 Subject: [Buildroot] [PATCH v2 1/2] arch: add support for RISC-V 32-bit (riscv32) architecture X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Corbin MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" This enables a riscv32 system to be built with a Buildroot generated toolchain (gcc >= 7.x, binutils >= 2.30, glibc only). This requires a custom version of glibc 2.26 from the riscv-glibc repository. Note that there are no tags in this repository, so the glibc version just consists of the 40 character commit id string. Thanks to Fabrice Bellard for pointing me towards the 32-bit glibc repository and for providing the necessary patch to get it to build. Signed-off-by: Mark Corbin Tested-by: Matt Weber --- Changes v1 -> v2: - regenerated the glibc patch correctly (Romain) - modified the conditional test for RISC-V 32-bit in glibc.mk to use the more consistent style for multiple variables (Romain) --- arch/Config.in.riscv | 23 +++++++- arch/arch.mk.riscv | 4 +- configs/qemu_riscv64_virt_defconfig | 1 + ...C-V-32-bit-build-of-riscv-glibc-2.26.patch | 59 +++++++++++++++++++ .../glibc.hash | 7 +++ package/glibc/glibc.mk | 7 +++ 6 files changed, 97 insertions(+), 4 deletions(-) create mode 100644 package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch create mode 100644 package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv index 4361890bf4..4615f3c797 100644 --- a/arch/Config.in.riscv +++ b/arch/Config.in.riscv @@ -66,13 +66,26 @@ config BR2_RISCV_ISA_CUSTOM_RVC endif config BR2_RISCV_64 - bool - default y + bool "64-bit" + default n select BR2_ARCH_IS_64 choice prompt "Target ABI" - default BR2_RISCV_ABI_LP64 + default BR2_RISCV_ABI_ILP32 if !BR2_ARCH_IS_64 + default BR2_RISCV_ABI_LP64 if BR2_ARCH_IS_64 + +config BR2_RISCV_ABI_ILP32 + bool "ilp32" + depends on !BR2_ARCH_IS_64 + +config BR2_RISCV_ABI_ILP32F + bool "ilp32f" + depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVF + +config BR2_RISCV_ABI_ILP32D + bool "ilp32d" + depends on !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD config BR2_RISCV_ABI_LP64 bool "lp64" @@ -88,12 +101,16 @@ config BR2_RISCV_ABI_LP64D endchoice config BR2_ARCH + default "riscv32" if !BR2_ARCH_IS_64 default "riscv64" if BR2_ARCH_IS_64 config BR2_ENDIAN default "LITTLE" config BR2_GCC_TARGET_ABI + default "ilp32" if BR2_RISCV_ABI_ILP32 + default "ilp32f" if BR2_RISCV_ABI_ILP32F + default "ilp32d" if BR2_RISCV_ABI_ILP32D default "lp64" if BR2_RISCV_ABI_LP64 default "lp64f" if BR2_RISCV_ABI_LP64F default "lp64d" if BR2_RISCV_ABI_LP64D diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv index 022d1a6809..f3bf2b3467 100644 --- a/arch/arch.mk.riscv +++ b/arch/arch.mk.riscv @@ -5,8 +5,10 @@ ifeq ($(BR2_riscv),y) -ifeq ($(BR2_ARCH_IS_64),y) +ifeq ($(BR2_RISCV_64),y) GCC_TARGET_ARCH := rv64i +else +GCC_TARGET_ARCH := rv32i endif ifeq ($(BR2_RISCV_ISA_RVM),y) diff --git a/configs/qemu_riscv64_virt_defconfig b/configs/qemu_riscv64_virt_defconfig index 59343ee98f..e15f804341 100644 --- a/configs/qemu_riscv64_virt_defconfig +++ b/configs/qemu_riscv64_virt_defconfig @@ -1,5 +1,6 @@ # Architecture BR2_riscv=y +BR2_RISCV_64=y # System BR2_SYSTEM_DHCP="eth0" diff --git a/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch new file mode 100644 index 0000000000..0596587ac5 --- /dev/null +++ b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/0001-Fix-RISC-V-32-bit-build-of-riscv-glibc-2.26.patch @@ -0,0 +1,59 @@ +From 4909cfbbe8dd512b8fc0892859549c26e1b14d30 Mon Sep 17 00:00:00 2001 +From: Mark Corbin +Date: Sun, 21 Oct 2018 10:38:18 +0100 +Subject: [PATCH 1/1] Fix RISC-V 32-bit build of riscv-glibc 2.26 + +This patch fixes two build errors with the 32-bit version of +glibc-2.26 from the riscv-glibc repository. + +A void reference to 'refsym' has been added to dl-runtime.c to avoid +an 'unused variable' error when building with '-Werror'. + +Some data types were hard-coded for 64-bit in ldsodefs.h. These have +been modified to allow 32-bit builds. + +This patch was provided by Fabrice Bellard as part of his RISC-V +Buildroot development source. + +Signed-off-by: Mark Corbin +--- + elf/dl-runtime.c | 1 + + sysdeps/riscv/ldsodefs.h | 4 ++-- + 2 files changed, 3 insertions(+), 2 deletions(-) + +diff --git a/elf/dl-runtime.c b/elf/dl-runtime.c +index 51d3819d4a..e728e8907e 100644 +--- a/elf/dl-runtime.c ++++ b/elf/dl-runtime.c +@@ -146,6 +146,7 @@ _dl_fixup ( + if (__glibc_unlikely (GLRO(dl_bind_not))) + return value; + ++ (void)refsym; + return elf_machine_fixup_plt (l, result, refsym, sym, reloc, rel_addr, value); + } + +diff --git a/sysdeps/riscv/ldsodefs.h b/sysdeps/riscv/ldsodefs.h +index db993df80a..91e7a8c88f 100644 +--- a/sysdeps/riscv/ldsodefs.h ++++ b/sysdeps/riscv/ldsodefs.h +@@ -25,14 +25,14 @@ struct La_riscv_regs; + struct La_riscv_retval; + + #define ARCH_PLTENTER_MEMBERS \ +- Elf64_Addr (*riscv_gnu_pltenter) (Elf64_Sym *, unsigned int, \ ++ ElfW(Addr) (*riscv_gnu_pltenter) (ElfW(Sym) *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + const struct La_riscv_regs *, \ + unsigned int *, const char *name, \ + long int *framesizep); + + #define ARCH_PLTEXIT_MEMBERS \ +- unsigned int (*riscv_gnu_pltexit) (Elf64_Sym *, unsigned int, \ ++ unsigned int (*riscv_gnu_pltexit) (ElfW(Sym) *, unsigned int, \ + uintptr_t *, uintptr_t *, \ + const struct La_riscv_regs *, \ + struct La_riscv_retval *, \ +-- +2.17.1 + diff --git a/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash new file mode 100644 index 0000000000..3eb5e04e96 --- /dev/null +++ b/package/glibc/4e2943456e690d89f48e6e710757dd09404b0c9a/glibc.hash @@ -0,0 +1,7 @@ +# Locally calculated (fetched from Github) +sha256 a40f908125135bad2cf92c18d07ad25b3091b161b3a5d3aea46c23ffd2ac90b8 glibc-4e2943456e690d89f48e6e710757dd09404b0c9a.tar.gz + +# Hashes for license files +sha256 8177f97513213526df2cf6184d8ff986c675afb514d4e68a404010521b880643 COPYING +sha256 dc626520dcd53a22f727af3ee42c770e56c97a64fe3adb063799d8ab032fe551 COPYING.LIB +sha256 61abdd6930c9c599062d89e916b3e7968783879b6be0ee1c6229dd6169def431 LICENSES diff --git a/package/glibc/glibc.mk b/package/glibc/glibc.mk index 708c22f723..408711bfb7 100644 --- a/package/glibc/glibc.mk +++ b/package/glibc/glibc.mk @@ -7,6 +7,9 @@ ifeq ($(BR2_arc),y) GLIBC_VERSION = arc-2018.03-release GLIBC_SITE = $(call github,foss-for-synopsys-dwc-arc-processors,glibc,$(GLIBC_VERSION)) +else ifeq ($(BR2_riscv):$(BR2_RISCV_64),y:) +GLIBC_VERSION = 4e2943456e690d89f48e6e710757dd09404b0c9a +GLIBC_SITE = $(call github,riscv,riscv-glibc,$(GLIBC_VERSION)) else # Generate version string using: # git describe --match 'glibc-*' --abbrev=40 origin/release/MAJOR.MINOR/master @@ -79,7 +82,11 @@ GLIBC_CONF_ENV = \ # Override the default library locations of /lib64/ and # /usr/lib64// for RISC-V. ifeq ($(BR2_riscv),y) +ifeq ($(BR2_RISCV_64),y) GLIBC_CONF_ENV += libc_cv_slibdir=/lib64 libc_cv_rtlddir=/lib +else +GLIBC_CONF_ENV += libc_cv_slibdir=/lib32 libc_cv_rtlddir=/lib +endif endif # Even though we use the autotools-package infrastructure, we have to