From patchwork Fri Jun 23 17:28:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vicente Olivert Riera X-Patchwork-Id: 780203 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wvQRC1bQRz9sxR for ; Sat, 24 Jun 2017 03:28:55 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by fraxinus.osuosl.org (Postfix) with ESMTP id F1D3D87A34; Fri, 23 Jun 2017 17:28:52 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from fraxinus.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0sfEmfaemlxu; Fri, 23 Jun 2017 17:28:49 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by fraxinus.osuosl.org (Postfix) with ESMTP id 8344C879DB; Fri, 23 Jun 2017 17:28:44 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 2FDF91C03CF for ; Fri, 23 Jun 2017 17:28:36 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 2AC9283B8B for ; Fri, 23 Jun 2017 17:28:36 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VJfGI8JUCyob for ; Fri, 23 Jun 2017 17:28:35 +0000 (UTC) X-Greylist: domain auto-whitelisted by SQLgrey-1.7.6 Received: from mailapp01.imgtec.com (mailapp01.imgtec.com [195.59.15.196]) by whitealder.osuosl.org (Postfix) with ESMTP id 573C283B14 for ; Fri, 23 Jun 2017 17:28:35 +0000 (UTC) Received: from HHMAIL01.hh.imgtec.org (unknown [10.100.10.19]) by Forcepoint Email with ESMTPS id 42ADFE2467DF9; Fri, 23 Jun 2017 18:28:29 +0100 (IST) Received: from vriera-linux.le.imgtec.org (192.168.154.36) by HHMAIL01.hh.imgtec.org (10.100.10.21) with Microsoft SMTP Server (TLS) id 14.3.294.0; Fri, 23 Jun 2017 18:28:33 +0100 From: Vicente Olivert Riera To: Date: Fri, 23 Jun 2017 18:28:25 +0100 Message-ID: <20170623172825.5778-4-Vincent.Riera@imgtec.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170623172825.5778-1-Vincent.Riera@imgtec.com> References: <20170623172825.5778-1-Vincent.Riera@imgtec.com> MIME-Version: 1.0 X-Originating-IP: [192.168.154.36] Cc: thomas.petazzoni@free-electrons.com Subject: [Buildroot] [PATCH v3 4/4] infra: add support for MIPS MSA X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: buildroot-bounces@busybox.net Sender: "buildroot" This patch adds support for MIPS SIMD Architecture (MSA) extension. This feature is available since MIPS release version 5 and is mutually exclusive with the MIPS DSP extension. Signed-off-by: Vicente Olivert Riera --- Changes v1 -> v3: - Nothing. Patch introduced in v3. --- arch/Config.in.mips | 21 +++++++++++++++++++++ .../toolchain-external/pkg-toolchain-external.mk | 4 ++++ toolchain/toolchain-wrapper.c | 3 +++ 3 files changed, 28 insertions(+) diff --git a/arch/Config.in.mips b/arch/Config.in.mips index 97d59acc8..1eb2cd158 100644 --- a/arch/Config.in.mips +++ b/arch/Config.in.mips @@ -23,6 +23,8 @@ config BR2_MIPS_CPU_HAS_DSP_R2 bool config BR2_MIPS_CPU_HAS_DSP_R3 bool +config BR2_MIPS_CPU_HAS_MSA + bool # some cpu features are optional depending on the core config BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 @@ -31,6 +33,8 @@ config BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 bool config BR2_MIPS_CPU_MAYBE_HAS_DSP_R3 bool +config BR2_MIPS_CPU_MAYBE_HAS_MSA + bool choice prompt "Target Architecture Variant" @@ -59,6 +63,7 @@ config BR2_mips_32r5 select BR2_MIPS_CPU_MIPS32R5 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_32r6 bool "Generic MIPS32R6" depends on !BR2_ARCH_IS_64 @@ -66,6 +71,7 @@ config BR2_mips_32r6 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_interaptiv bool "interAptiv" depends on !BR2_ARCH_IS_64 @@ -87,6 +93,7 @@ config BR2_mips_p5600 depends on !BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS32R5 select BR2_MIPS_NAN_2008 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_xburst bool "XBurst" depends on !BR2_ARCH_IS_64 @@ -116,6 +123,7 @@ config BR2_mips_64r5 select BR2_MIPS_CPU_MIPS64R5 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_64r6 bool "Generic MIPS64R6" depends on BR2_ARCH_IS_64 @@ -123,14 +131,17 @@ config BR2_mips_64r6 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R1 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R2 select BR2_MIPS_CPU_MAYBE_HAS_DSP_R3 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_i6400 bool "I6400" depends on BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS64R6 + select BR2_MIPS_CPU_MAYBE_HAS_MSA config BR2_mips_p6600 bool "P6600" depends on BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS64R6 + select BR2_MIPS_CPU_MAYBE_HAS_MSA endchoice @@ -252,6 +263,16 @@ config BR2_GCC_TARGET_DSP default "dspr2" if BR2_MIPS_CPU_HAS_DSP_R2 default "dspr3" if BR2_MIPS_CPU_HAS_DSP_R3 +config BR2_MIPS_ENABLE_MSA + bool "Enable MSA extension support" + depends on BR2_MIPS_CPU_MAYBE_HAS_MSA && BR2_MIPS_FP32_MODE_64 + depends on !(BR2_MIPS_CPU_HAS_DSP_R1 || BR2_MIPS_CPU_HAS_DSP_R2 || BR2_MIPS_CPU_HAS_DSP_R3) + select BR2_MIPS_CPU_HAS_MSA + help + For some CPU cores, the MSA extension is optional. + Select this option if you are certain your particular + implementation has MSA support and you want to use it. + config BR2_ARCH default "mips" if BR2_mips default "mipsel" if BR2_mipsel diff --git a/toolchain/toolchain-external/pkg-toolchain-external.mk b/toolchain/toolchain-external/pkg-toolchain-external.mk index ce3a48db8..28dca1690 100644 --- a/toolchain/toolchain-external/pkg-toolchain-external.mk +++ b/toolchain/toolchain-external/pkg-toolchain-external.mk @@ -189,6 +189,10 @@ ifneq ($(CC_TARGET_DSP_),) TOOLCHAIN_EXTERNAL_CFLAGS += -m$(CC_TARGET_DSP_) TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_DSP='"$(CC_TARGET_DSP_)"' endif +ifneq ($(BR2_MIPS_CPU_HAS_MSA),) +TOOLCHAIN_EXTERNAL_CFLAGS += -mmsa +TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_MSA +endif ifneq ($(CC_TARGET_FP32_MODE_),) TOOLCHAIN_EXTERNAL_CFLAGS += -mfp$(CC_TARGET_FP32_MODE_) TOOLCHAIN_EXTERNAL_TOOLCHAIN_WRAPPER_ARGS += -DBR_FP32_MODE='"$(CC_TARGET_FP32_MODE_)"' diff --git a/toolchain/toolchain-wrapper.c b/toolchain/toolchain-wrapper.c index 670e00884..3e001e6ea 100644 --- a/toolchain/toolchain-wrapper.c +++ b/toolchain/toolchain-wrapper.c @@ -57,6 +57,9 @@ static char *predef_args[] = { #ifdef BR_DSP "-m" BR_DSP, #endif +#ifdef BR_MSA + "-mmsa", +#endif #ifdef BR_FPU "-mfpu=" BR_FPU, #endif