From patchwork Sun Dec 9 21:54:03 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gustavo Zacarias X-Patchwork-Id: 204792 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from silver.osuosl.org (silver.osuosl.org [140.211.166.136]) by ozlabs.org (Postfix) with ESMTP id 106402C01E5 for ; Mon, 10 Dec 2012 08:54:23 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by silver.osuosl.org (Postfix) with ESMTP id 080F83106B; Sun, 9 Dec 2012 21:54:22 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from silver.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5S8cnFlmDVSP; Sun, 9 Dec 2012 21:54:19 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by silver.osuosl.org (Postfix) with ESMTP id 834813107E; Sun, 9 Dec 2012 21:54:19 +0000 (UTC) X-Original-To: buildroot@lists.busybox.net Delivered-To: buildroot@osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 24E798F74B for ; Sun, 9 Dec 2012 21:54:24 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 0B80C80820 for ; Sun, 9 Dec 2012 21:54:19 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PllfMAG1QF4r for ; Sun, 9 Dec 2012 21:54:18 +0000 (UTC) X-Greylist: from auto-whitelisted by SQLgrey-1.7.6 Received: from loknar.toptech.com.ar (loknar.toptech.com.ar [78.46.79.162]) by whitealder.osuosl.org (Postfix) with ESMTPS id E25C980663 for ; Sun, 9 Dec 2012 21:54:17 +0000 (UTC) Received: from asgard (host201.201-252-64.telecom.net.ar [201.252.64.201]) (authenticated bits=0) by loknar.toptech.com.ar (8.14.5/8.14.5) with ESMTP id qB9LsB0d024587 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 9 Dec 2012 21:54:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=zacarias.com.ar; s=dkey; t=1355090055; bh=hOhNDSE4o7OgIR73C6hTXwFkQ/cwiHKI1Kog7H9aKls=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=v4NrNWpJFU853XiH5i7a5YymxM6Hk0PXoEKyTaPrKIUKzxVnAzfkKuEA0pxHiyVis DP7Nh1+njIoDAsySvOT2uGQ9vdsASEcZerDGGKeSFlAMEod+0qD7gCTth3b8Vbf6Yr UEGftZYigRkuTeBoIiXby1jwaxBbj102wzWlwocE= Received: by asgard (sSMTP sendmail emulation); Sun, 09 Dec 2012 18:54:10 -0300 From: Gustavo Zacarias To: buildroot@busybox.net Date: Sun, 9 Dec 2012 18:54:03 -0300 Message-Id: <1355090043-12326-2-git-send-email-gustavo@zacarias.com.ar> X-Mailer: git-send-email 1.7.8.6 In-Reply-To: <1355090043-12326-1-git-send-email-gustavo@zacarias.com.ar> References: <1355090043-12326-1-git-send-email-gustavo@zacarias.com.ar> X-Virus-Scanned: clamav-milter 0.97.5 at loknar X-Virus-Status: Clean Subject: [Buildroot] [PATCH 2/2] arm: update processor types X-BeenThere: buildroot@busybox.net X-Mailman-Version: 2.1.14 Precedence: list List-Id: Discussion and development of buildroot List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: buildroot-bounces@busybox.net Sender: buildroot-bounces@busybox.net Update the arm processor types: add the cortex A5 & A15 variants. Signed-off-by: Gustavo Zacarias --- arch/Config.in.arm | 8 ++++++++ toolchain/gcc/Config.in | 6 +++--- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/Config.in.arm b/arch/Config.in.arm index 6e5d258..b65b4ac 100644 --- a/arch/Config.in.arm +++ b/arch/Config.in.arm @@ -29,10 +29,14 @@ config BR2_arm1176jz_s bool "arm1176jz-s" config BR2_arm1176jzf_s bool "arm1176jzf-s" +config BR2_cortex_a5 + bool "cortex-A5" config BR2_cortex_a8 bool "cortex-A8" config BR2_cortex_a9 bool "cortex-A9" +config BR2_cortex_a15 + bool "cortex-A15" config BR2_sa110 bool "sa110" config BR2_sa1100 @@ -83,8 +87,10 @@ config BR2_GCC_TARGET_TUNE default "arm1136jf-s" if BR2_arm1136jf_s default "arm1176jz-s" if BR2_arm1176jz_s default "arm1176jzf-s" if BR2_arm1176jzf_s + default "cortex-a5" if BR2_cortex_a5 default "cortex-a8" if BR2_cortex_a8 default "cortex-a9" if BR2_cortex_a9 + default "cortex-a15" if BR2_cortex_a15 default "strongarm110" if BR2_sa110 default "strongarm1100" if BR2_sa1100 default "xscale" if BR2_xscale @@ -102,8 +108,10 @@ config BR2_GCC_TARGET_ARCH default "armv6j" if BR2_arm1136jf_s default "armv6zk" if BR2_arm1176jz_s default "armv6zk" if BR2_arm1176jzf_s + default "armv7-a" if BR2_cortex_a5 default "armv7-a" if BR2_cortex_a8 default "armv7-a" if BR2_cortex_a9 + default "armv7-a" if BR2_cortex_a15 default "armv4" if BR2_sa110 default "armv4" if BR2_sa1100 default "armv5te" if BR2_xscale diff --git a/toolchain/gcc/Config.in b/toolchain/gcc/Config.in index de79452..d16e7b0 100644 --- a/toolchain/gcc/Config.in +++ b/toolchain/gcc/Config.in @@ -15,15 +15,15 @@ choice bool "gcc 4.2.2-avr32-2.1.5" config BR2_GCC_VERSION_4_3_X - depends on !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_x86_atom && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp + depends on !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 && !BR2_cortex_a5 && !BR2_cortex_a8 && !BR2_cortex_a9 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_e300c2 && !BR2_powerpc_e300c3 && !BR2_powerpc_e500mc && !BR2_powerpc_464 && !BR2_powerpc_464fp && !BR2_powerpc_476 && !BR2_powerpc_476fp bool "gcc 4.3.x" config BR2_GCC_VERSION_4_4_X - depends on !BR2_avr32 && !BR2_x86_atom && !BR2_powerpc_476 && !BR2_powerpc_476fp + depends on !BR2_avr32 && !BR2_cortex_a5 && !BR2_cortex_a15 && !BR2_x86_atom && !BR2_powerpc_476 && !BR2_powerpc_476fp bool "gcc 4.4.x" config BR2_GCC_VERSION_4_5_X - depends on !BR2_avr32 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 + depends on !BR2_avr32 && !BR2_cortex_a15 && !BR2_sparc_sparchfleon && !BR2_sparc_sparchfleonv8 && !BR2_sparc_sparcsfleon && !BR2_sparc_sparcsfleonv8 bool "gcc 4.5.x" config BR2_GCC_VERSION_4_6_X