| Message ID | 1419245190-23604-1-git-send-email-jy0922.shim@samsung.com |
|---|---|
| State | Accepted |
| Delegated to: | Minkyu Kang |
| Headers | show |
Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung On 12/22/2014 07:46 PM, Joonyoung Shim wrote: > MMC of exynos5420 can select SPLL as source clock, so add to support > SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. > > Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> > --- > arch/arm/cpu/armv7/exynos/clock.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index 8fab135..b31c13b 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index) > > if (sel == 0x3) > sclk = get_pll_clk(MPLL); > + else if (sel == 0x4) > + sclk = get_pll_clk(SPLL); > else if (sel == 0x6) > sclk = get_pll_clk(EPLL); > else >
On 22/12/14 19:46, Joonyoung Shim wrote: > MMC of exynos5420 can select SPLL as source clock, so add to support > SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. > > Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> > --- > arch/arm/cpu/armv7/exynos/clock.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index 8fab135..b31c13b 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index) > > if (sel == 0x3) > sclk = get_pll_clk(MPLL); > + else if (sel == 0x4) > + sclk = get_pll_clk(SPLL); > else if (sel == 0x6) > sclk = get_pll_clk(EPLL); > else > applied to u-boot-samsung. Thanks, Minkyu Kang.
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 8fab135..b31c13b 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -848,6 +848,8 @@ static unsigned long exynos5420_get_mmc_clk(int dev_index) if (sel == 0x3) sclk = get_pll_clk(MPLL); + else if (sel == 0x4) + sclk = get_pll_clk(SPLL); else if (sel == 0x6) sclk = get_pll_clk(EPLL); else
MMC of exynos5420 can select SPLL as source clock, so add to support SPLL in exynos5420_get_mmc_clk(). It was tested on Odroid-XU3 board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> --- arch/arm/cpu/armv7/exynos/clock.c | 2 ++ 1 file changed, 2 insertions(+)