| Message ID | 1417788802-13219-1-git-send-email-festevam@gmail.com |
|---|---|
| State | New |
| Headers | show |
On Fri, Dec 05, 2014 at 12:13:20PM -0200, Fabio Estevam wrote: > From: Fabio Estevam <fabio.estevam@freescale.com> > > Provide a proper parent for QSPI clocks to avoid a kernel oops: > > [ 1.037920] Division by zero in kernel. What is the original parent clock, and how does that cause a division by zero error? Shawn > [ 1.041807] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.18.0-rc7-next-20141204-00002-g5aa23e1 #2143 > [ 1.050967] Hardware name: Freescale i.MX6 SoloX (Device Tree) > [ 1.056853] Backtrace: > [ 1.059360] [<80011ea0>] (dump_backtrace) from [<8001203c>] (show_stack+0x18/0x1c) > [ 1.066982] r6:00000000 r5:00000000 r4:00000000 r3:00000000 > [ 1.072754] [<80012024>] (show_stack) from [<806b7100>] (dump_stack+0x88/0xa4) > [ 1.080038] [<806b7078>] (dump_stack) from [<80011d20>] (__div0+0x18/0x20) > [ 1.086958] r5:be018500 r4:be017c00 > [ 1.090600] [<80011d08>] (__div0) from [<802aa418>] (Ldiv0+0x8/0x10) > [ 1.097012] [<80504fbc>] (clk_divider_set_rate) from [<80503ddc>] (clk_change_rate+0x14c/0x17c) > [ 1.105759] r7:00000000 r6:00000000 r5:be018500 r4:00000000 > [ 1.111516] [<80503c90>] (clk_change_rate) from [<80503ea0>] (clk_set_rate+0x94/0x98) > [ 1.119391] r8:be7e0368 r7:00000000 r6:be11a000 r5:be018500 r4:00000000 r3:00000000 > [ 1.127290] [<80503e0c>] (clk_set_rate) from [<80410558>] (fsl_qspi_probe+0x23c/0x75c) > [ 1.135260] r5:be11a010 r4:be350010 > [ 1.138900] [<8041031c>] (fsl_qspi_probe) from [<80385a18>] (platform_drv_probe+0x50/0xac) > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- > arch/arm/mach-imx/clk-imx6sx.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c > index 17354a1..5a3e5a1 100644 > --- a/arch/arm/mach-imx/clk-imx6sx.c > +++ b/arch/arm/mach-imx/clk-imx6sx.c > @@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) > clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); > clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); > > + clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); > + clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); > + > /* Set initial power mode */ > imx6q_set_lpm(WAIT_CLOCKED); > } > -- > 1.9.1 >
Hi Shawn, On Tue, Dec 16, 2014 at 5:29 AM, Shawn Guo <shawn.guo@linaro.org> wrote: > What is the original parent clock, and how does that cause a division by > zero error? The default qspi2_clk_sel contains '110' which is marked as 'reserved' in the reference manual. This causes the qspi2 to look like this in the clock tree: dummy 4 4 0 0 qspi2_sel 1 1 0 0 qspi2_pred 1 1 0 0 qspi2_podf 1 1 0 0 gpmi_io 0 0 0 0 qspi2 1 1 0 A 'dummy' clock gets assigned as parent. This is will cause the division by zero when the qspi driver calls clk_set_rate(). I will send a v2 with such explanation.
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c index 17354a1..5a3e5a1 100644 --- a/arch/arm/mach-imx/clk-imx6sx.c +++ b/arch/arm/mach-imx/clk-imx6sx.c @@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); + clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]); + /* Set initial power mode */ imx6q_set_lpm(WAIT_CLOCKED); }