| Message ID | 1417570823-19977-1-git-send-email-davidu@nvidia.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Fri, Dec 05, 2014 at 01:48:42PM -0800, Sean Paul wrote: > On Tue, Dec 2, 2014 at 5:40 PM, David Ung <davidu@nvidia.com> wrote: > > > Fix DSI PHY HS Trail setting on Tegra. > > It is found that HS Trail is off -12% during compliance testing > > > > > [this time from the correct email address] > > Our timing tests pass now. > > Tested-by: Sean Paul <seanpaul@chromium.org> Can describe what kinds of timing tests these are? I obviously lack the kind of equipment for this, but I'd still like to know how you get these results. Thierry
The subject prefix should be "drm/tegra: dsi:". Also make sure to use the proper case. "dsi" should be "DSI" and "phy" should be "PHY". Also the DSI PHY is typically referred to as D-PHY, so a better subject would be: drm/tegra: dsi: Adjust D-PHY timing One more comment below: On Tue, Dec 02, 2014 at 05:40:23PM -0800, David Ung wrote: > Fix DSI PHY HS Trail setting on Tegra. > It is found that HS Trail is off -12% during compliance testing > > Signed-off-by: David Ung <davidu@nvidia.com> > --- > drivers/gpu/drm/tegra/mipi-phy.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/tegra/mipi-phy.c b/drivers/gpu/drm/tegra/mipi-phy.c > index 486d19d..974bc68 100644 > --- a/drivers/gpu/drm/tegra/mipi-phy.c > +++ b/drivers/gpu/drm/tegra/mipi-phy.c > @@ -34,7 +34,7 @@ int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, > timing->hszero = 145 + 5 * period; > timing->hssettle = 85 + 6 * period; > timing->hsskip = 40; > - timing->hstrail = max(8 * period, 60 + 4 * period); > + timing->hstrail = 3 * period * 8 + max(8 * period, 60 + 4 * period); > timing->init = 100000; > timing->lpx = 60; > timing->taget = 5 * timing->lpx; Back when I wrote this code I envisioned that this could eventually be a generic set of helpers that could be used across different DSI drivers. As such, mipi_dphy_timing_get_default() obtains the default timings as given by the D-PHY specification. Therefore you should be adjusting this within the driver code rather than the default timings. And then make it something like: /* comment explaining why this is needed */ timing.hstrail += 3 * period * 8; That said, most of this code is in flux right now, so I probably have to manually apply the patch. It would still be good to respin with these comments addressed so that I can adopt the commit message and comment explaining why this is necessary or what the consequences are. Thierry
diff --git a/drivers/gpu/drm/tegra/mipi-phy.c b/drivers/gpu/drm/tegra/mipi-phy.c index 486d19d..974bc68 100644 --- a/drivers/gpu/drm/tegra/mipi-phy.c +++ b/drivers/gpu/drm/tegra/mipi-phy.c @@ -34,7 +34,7 @@ int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, timing->hszero = 145 + 5 * period; timing->hssettle = 85 + 6 * period; timing->hsskip = 40; - timing->hstrail = max(8 * period, 60 + 4 * period); + timing->hstrail = 3 * period * 8 + max(8 * period, 60 + 4 * period); timing->init = 100000; timing->lpx = 60; timing->taget = 5 * timing->lpx;
Fix DSI PHY HS Trail setting on Tegra. It is found that HS Trail is off -12% during compliance testing Signed-off-by: David Ung <davidu@nvidia.com> --- drivers/gpu/drm/tegra/mipi-phy.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)