@@ -113,20 +113,20 @@
BUILTIN_VQW (BINOP, ssubw2, 0)
BUILTIN_VQW (BINOP, usubw2, 0)
/* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>. */
- BUILTIN_VDW (BINOP, saddl, 0)
- BUILTIN_VDW (BINOP, uaddl, 0)
- BUILTIN_VDW (BINOP, ssubl, 0)
- BUILTIN_VDW (BINOP, usubl, 0)
+ BUILTIN_VD_BHSI (BINOP, saddl, 0)
+ BUILTIN_VD_BHSI (BINOP, uaddl, 0)
+ BUILTIN_VD_BHSI (BINOP, ssubl, 0)
+ BUILTIN_VD_BHSI (BINOP, usubl, 0)
/* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>. */
- BUILTIN_VDW (BINOP, saddw, 0)
- BUILTIN_VDW (BINOP, uaddw, 0)
- BUILTIN_VDW (BINOP, ssubw, 0)
- BUILTIN_VDW (BINOP, usubw, 0)
+ BUILTIN_VD_BHSI (BINOP, saddw, 0)
+ BUILTIN_VD_BHSI (BINOP, uaddw, 0)
+ BUILTIN_VD_BHSI (BINOP, ssubw, 0)
+ BUILTIN_VD_BHSI (BINOP, usubw, 0)
/* Implemented by aarch64_<sur>h<addsub><mode>. */
- BUILTIN_VQ_S (BINOP, shadd, 0)
- BUILTIN_VQ_S (BINOP, uhadd, 0)
- BUILTIN_VQ_S (BINOP, srhadd, 0)
- BUILTIN_VQ_S (BINOP, urhadd, 0)
+ BUILTIN_VDQ_BHSI (BINOP, shadd, 0)
+ BUILTIN_VDQ_BHSI (BINOP, uhadd, 0)
+ BUILTIN_VDQ_BHSI (BINOP, srhadd, 0)
+ BUILTIN_VDQ_BHSI (BINOP, urhadd, 0)
/* Implemented by aarch64_<sur><addsub>hn<mode>. */
BUILTIN_VQN (BINOP, addhn, 0)
BUILTIN_VQN (BINOP, raddhn, 0)
@@ -200,8 +200,8 @@
BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
/* Implemented by aarch64_<sur>shll_n<mode>. */
- BUILTIN_VDW (SHIFTIMM, sshll_n, 0)
- BUILTIN_VDW (USHIFTIMM, ushll_n, 0)
+ BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0)
+ BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0)
/* Implemented by aarch64_<sur>shll2_n<mode>. */
BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
@@ -42,8 +42,9 @@
})
(define_insn "aarch64_simd_dup<mode>"
- [(set (match_operand:VDQ 0 "register_operand" "=w, w")
- (vec_duplicate:VDQ (match_operand:<VEL> 1 "register_operand" "r, w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w, w")
+ (vec_duplicate:VDQ_I
+ (match_operand:<VEL> 1 "register_operand" "r, w")))]
"TARGET_SIMD"
"@
dup\\t%0.<Vtype>, %<vw>1
@@ -242,45 +243,45 @@
])
(define_insn "orn<mode>3"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (ior:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w"))
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (ior:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"orn\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
(define_insn "bic<mode>3"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (and:VDQ (not:VDQ (match_operand:VDQ 1 "register_operand" "w"))
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (and:VDQ_I (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w"))
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"bic\t%0.<Vbtype>, %2.<Vbtype>, %1.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
(define_insn "add<mode>3"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (plus:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (plus:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"add\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_add<q>")]
)
(define_insn "sub<mode>3"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (minus:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (minus:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"sub\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_sub<q>")]
)
(define_insn "mul<mode>3"
- [(set (match_operand:VDQM 0 "register_operand" "=w")
- (mult:VDQM (match_operand:VDQM 1 "register_operand" "w")
- (match_operand:VDQM 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (mult:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))]
"TARGET_SIMD"
"mul\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_mul_<Vetype><q>")]
@@ -363,16 +364,16 @@
)
(define_insn "neg<mode>2"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (neg:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (neg:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))]
"TARGET_SIMD"
"neg\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "type" "neon_neg<q>")]
)
(define_insn "abs<mode>2"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (abs:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (abs:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))]
"TARGET_SIMD"
"abs\t%0.<Vtype>, %1.<Vtype>"
[(set_attr "type" "neon_abs<q>")]
@@ -420,46 +421,46 @@
)
(define_insn "and<mode>3"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (and:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (and:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"and\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
(define_insn "ior<mode>3"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (ior:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (ior:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"orr\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
(define_insn "xor<mode>3"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (xor:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (xor:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"eor\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
(define_insn "one_cmpl<mode>2"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (not:VDQ (match_operand:VDQ 1 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (not:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")))]
"TARGET_SIMD"
"not\t%0.<Vbtype>, %1.<Vbtype>"
[(set_attr "type" "neon_logic<q>")]
)
(define_insn "aarch64_simd_vec_set<mode>"
- [(set (match_operand:VQ_S 0 "register_operand" "=w,w")
- (vec_merge:VQ_S
- (vec_duplicate:VQ_S
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w,w")
+ (vec_merge:VDQ_BHSI
+ (vec_duplicate:VDQ_BHSI
(match_operand:<VEL> 1 "register_operand" "r,w"))
- (match_operand:VQ_S 3 "register_operand" "0,0")
+ (match_operand:VDQ_BHSI 3 "register_operand" "0,0")
(match_operand:SI 2 "immediate_operand" "i,i")))]
"TARGET_SIMD"
{
@@ -479,45 +480,45 @@
)
(define_insn "aarch64_simd_lshr<mode>"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (lshiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (lshiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "aarch64_simd_rshift_imm" "Dr")))]
"TARGET_SIMD"
"ushr\t%0.<Vtype>, %1.<Vtype>, %2"
[(set_attr "type" "neon_shift_imm<q>")]
)
(define_insn "aarch64_simd_ashr<mode>"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (ashiftrt:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "aarch64_simd_rshift_imm" "Dr")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (ashiftrt:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "aarch64_simd_rshift_imm" "Dr")))]
"TARGET_SIMD"
"sshr\t%0.<Vtype>, %1.<Vtype>, %2"
[(set_attr "type" "neon_shift_imm<q>")]
)
(define_insn "aarch64_simd_imm_shl<mode>"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (ashift:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "aarch64_simd_lshift_imm" "Dl")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (ashift:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "aarch64_simd_lshift_imm" "Dl")))]
"TARGET_SIMD"
"shl\t%0.<Vtype>, %1.<Vtype>, %2"
[(set_attr "type" "neon_shift_imm<q>")]
)
(define_insn "aarch64_simd_reg_sshl<mode>"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (ashift:VDQ (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (ashift:VDQ_I (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")))]
"TARGET_SIMD"
"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_shift_reg<q>")]
)
(define_insn "aarch64_simd_reg_shl<mode>_unsigned"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")]
UNSPEC_ASHIFT_UNSIGNED))]
"TARGET_SIMD"
"ushl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
@@ -525,9 +526,9 @@
)
(define_insn "aarch64_simd_reg_shl<mode>_signed"
- [(set (match_operand:VDQ 0 "register_operand" "=w")
- (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")]
+ [(set (match_operand:VDQ_I 0 "register_operand" "=w")
+ (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")]
UNSPEC_ASHIFT_SIGNED))]
"TARGET_SIMD"
"sshl\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
@@ -535,8 +536,8 @@
)
(define_expand "ashl<mode>3"
- [(match_operand:VDQ 0 "register_operand" "")
- (match_operand:VDQ 1 "register_operand" "")
+ [(match_operand:VDQ_I 0 "register_operand" "")
+ (match_operand:VDQ_I 1 "register_operand" "")
(match_operand:SI 2 "general_operand" "")]
"TARGET_SIMD"
{
@@ -582,8 +583,8 @@
)
(define_expand "lshr<mode>3"
- [(match_operand:VDQ 0 "register_operand" "")
- (match_operand:VDQ 1 "register_operand" "")
+ [(match_operand:VDQ_I 0 "register_operand" "")
+ (match_operand:VDQ_I 1 "register_operand" "")
(match_operand:SI 2 "general_operand" "")]
"TARGET_SIMD"
{
@@ -629,8 +630,8 @@
)
(define_expand "ashr<mode>3"
- [(match_operand:VDQ 0 "register_operand" "")
- (match_operand:VDQ 1 "register_operand" "")
+ [(match_operand:VDQ_I 0 "register_operand" "")
+ (match_operand:VDQ_I 1 "register_operand" "")
(match_operand:SI 2 "general_operand" "")]
"TARGET_SIMD"
{
@@ -676,9 +677,9 @@
)
(define_expand "vashl<mode>3"
- [(match_operand:VDQ 0 "register_operand" "")
- (match_operand:VDQ 1 "register_operand" "")
- (match_operand:VDQ 2 "register_operand" "")]
+ [(match_operand:VDQ_I 0 "register_operand" "")
+ (match_operand:VDQ_I 1 "register_operand" "")
+ (match_operand:VDQ_I 2 "register_operand" "")]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1],
@@ -686,13 +687,13 @@
DONE;
})
-;; Using mode VQ_S as there is no V2DImode neg!
+;; Using mode VDQ_BHSI as there is no V2DImode neg!
;; Negating individual lanes most certainly offsets the
;; gain from vectorization.
(define_expand "vashr<mode>3"
- [(match_operand:VQ_S 0 "register_operand" "")
- (match_operand:VQ_S 1 "register_operand" "")
- (match_operand:VQ_S 2 "register_operand" "")]
+ [(match_operand:VDQ_BHSI 0 "register_operand" "")
+ (match_operand:VDQ_BHSI 1 "register_operand" "")
+ (match_operand:VDQ_BHSI 2 "register_operand" "")]
"TARGET_SIMD"
{
rtx neg = gen_reg_rtx (<MODE>mode);
@@ -729,9 +730,9 @@
)
(define_expand "vlshr<mode>3"
- [(match_operand:VQ_S 0 "register_operand" "")
- (match_operand:VQ_S 1 "register_operand" "")
- (match_operand:VQ_S 2 "register_operand" "")]
+ [(match_operand:VDQ_BHSI 0 "register_operand" "")
+ (match_operand:VDQ_BHSI 1 "register_operand" "")
+ (match_operand:VDQ_BHSI 2 "register_operand" "")]
"TARGET_SIMD"
{
rtx neg = gen_reg_rtx (<MODE>mode);
@@ -767,7 +768,7 @@
)
(define_expand "vec_set<mode>"
- [(match_operand:VQ_S 0 "register_operand")
+ [(match_operand:VDQ_BHSI 0 "register_operand")
(match_operand:<VEL> 1 "register_operand")
(match_operand:SI 2 "immediate_operand")]
"TARGET_SIMD"
@@ -848,10 +849,11 @@
(define_insn "aarch64_mla<mode>"
- [(set (match_operand:VQ_S 0 "register_operand" "=w")
- (plus:VQ_S (mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w")
- (match_operand:VQ_S 3 "register_operand" "w"))
- (match_operand:VQ_S 1 "register_operand" "0")))]
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (plus:VDQ_BHSI (mult:VDQ_BHSI
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")
+ (match_operand:VDQ_BHSI 3 "register_operand" "w"))
+ (match_operand:VDQ_BHSI 1 "register_operand" "0")))]
"TARGET_SIMD"
"mla\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "type" "neon_mla_<Vetype><q>")]
@@ -895,10 +897,10 @@
)
(define_insn "aarch64_mls<mode>"
- [(set (match_operand:VQ_S 0 "register_operand" "=w")
- (minus:VQ_S (match_operand:VQ_S 1 "register_operand" "0")
- (mult:VQ_S (match_operand:VQ_S 2 "register_operand" "w")
- (match_operand:VQ_S 3 "register_operand" "w"))))]
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (minus:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "0")
+ (mult:VDQ_BHSI (match_operand:VDQ_BHSI 2 "register_operand" "w")
+ (match_operand:VDQ_BHSI 3 "register_operand" "w"))))]
"TARGET_SIMD"
"mls\t%0.<Vtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "type" "neon_mla_<Vetype><q>")]
@@ -943,9 +945,9 @@
;; Max/Min operations.
(define_insn "<su><maxmin><mode>3"
- [(set (match_operand:VQ_S 0 "register_operand" "=w")
- (MAXMIN:VQ_S (match_operand:VQ_S 1 "register_operand" "w")
- (match_operand:VQ_S 2 "register_operand" "w")))]
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (MAXMIN:VDQ_BHSI (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))]
"TARGET_SIMD"
"<su><maxmin>\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_minmax<q>")]
@@ -1250,9 +1252,9 @@
(plus:<VWIDE>
(mult:<VWIDE>
(ANY_EXTEND:<VWIDE>
- (match_operand:VDW 1 "register_operand" "w"))
+ (match_operand:VD_BHSI 1 "register_operand" "w"))
(ANY_EXTEND:<VWIDE>
- (match_operand:VDW 2 "register_operand" "w")))
+ (match_operand:VD_BHSI 2 "register_operand" "w")))
(match_operand:<VWIDE> 3 "register_operand" "0")))]
"TARGET_SIMD"
"<su>mlal\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
@@ -1265,9 +1267,9 @@
(match_operand:<VWIDE> 1 "register_operand" "0")
(mult:<VWIDE>
(ANY_EXTEND:<VWIDE>
- (match_operand:VDW 2 "register_operand" "w"))
+ (match_operand:VD_BHSI 2 "register_operand" "w"))
(ANY_EXTEND:<VWIDE>
- (match_operand:VDW 3 "register_operand" "w")))))]
+ (match_operand:VD_BHSI 3 "register_operand" "w")))))]
"TARGET_SIMD"
"<su>mlsl\t%0.<Vwtype>, %2.<Vtype>, %3.<Vtype>"
[(set_attr "type" "neon_mla_<Vetype>_long")]
@@ -1762,7 +1764,7 @@
(define_expand "reduc_plus_scal_<mode>"
[(match_operand:<VEL> 0 "register_operand" "=w")
- (unspec:VDQ [(match_operand:VDQ 1 "register_operand" "w")]
+ (unspec:VDQ_I [(match_operand:VDQ_I 1 "register_operand" "w")]
UNSPEC_ADDV)]
"TARGET_SIMD"
{
@@ -1957,13 +1959,13 @@
})
(define_expand "aarch64_vcond_internal<mode><mode>"
- [(set (match_operand:VDQ 0 "register_operand")
- (if_then_else:VDQ
+ [(set (match_operand:VDQ_I 0 "register_operand")
+ (if_then_else:VDQ_I
(match_operator 3 "comparison_operator"
- [(match_operand:VDQ 4 "register_operand")
- (match_operand:VDQ 5 "nonmemory_operand")])
- (match_operand:VDQ 1 "nonmemory_operand")
- (match_operand:VDQ 2 "nonmemory_operand")))]
+ [(match_operand:VDQ_I 4 "register_operand")
+ (match_operand:VDQ_I 5 "nonmemory_operand")])
+ (match_operand:VDQ_I 1 "nonmemory_operand")
+ (match_operand:VDQ_I 2 "nonmemory_operand")))]
"TARGET_SIMD"
{
rtx op1 = operands[1];
@@ -2298,13 +2300,13 @@
})
(define_expand "vcondu<mode><mode>"
- [(set (match_operand:VDQ 0 "register_operand")
- (if_then_else:VDQ
+ [(set (match_operand:VDQ_I 0 "register_operand")
+ (if_then_else:VDQ_I
(match_operator 3 "comparison_operator"
- [(match_operand:VDQ 4 "register_operand")
- (match_operand:VDQ 5 "nonmemory_operand")])
- (match_operand:VDQ 1 "nonmemory_operand")
- (match_operand:VDQ 2 "nonmemory_operand")))]
+ [(match_operand:VDQ_I 4 "register_operand")
+ (match_operand:VDQ_I 5 "nonmemory_operand")])
+ (match_operand:VDQ_I 1 "nonmemory_operand")
+ (match_operand:VDQ_I 2 "nonmemory_operand")))]
"TARGET_SIMD"
{
emit_insn (gen_aarch64_vcond_internal<mode><mode> (operands[0], operands[1],
@@ -2410,8 +2412,8 @@
(define_insn "*aarch64_combinez<mode>"
[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
(vec_concat:<VDBL>
- (match_operand:VDIC 1 "register_operand" "w")
- (match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")))]
+ (match_operand:VD_BHSI 1 "register_operand" "w")
+ (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")))]
"TARGET_SIMD && !BYTES_BIG_ENDIAN"
"mov\\t%0.8b, %1.8b"
[(set_attr "type" "neon_move<q>")]
@@ -2420,8 +2422,8 @@
(define_insn "*aarch64_combinez_be<mode>"
[(set (match_operand:<VDBL> 0 "register_operand" "=&w")
(vec_concat:<VDBL>
- (match_operand:VDIC 2 "aarch64_simd_imm_zero" "Dz")
- (match_operand:VDIC 1 "register_operand" "w")))]
+ (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")
+ (match_operand:VD_BHSI 1 "register_operand" "w")))]
"TARGET_SIMD && BYTES_BIG_ENDIAN"
"mov\\t%0.8b, %1.8b"
[(set_attr "type" "neon_move<q>")]
@@ -2560,9 +2562,9 @@
(define_insn "aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (ANY_EXTEND:<VWIDE>
- (match_operand:VDW 1 "register_operand" "w"))
+ (match_operand:VD_BHSI 1 "register_operand" "w"))
(ANY_EXTEND:<VWIDE>
- (match_operand:VDW 2 "register_operand" "w"))))]
+ (match_operand:VD_BHSI 2 "register_operand" "w"))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>l %0.<Vwtype>, %1.<Vtype>, %2.<Vtype>"
[(set_attr "type" "neon_<ADDSUB:optab>_long")]
@@ -2574,7 +2576,7 @@
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
(ADDSUB:<VWIDE> (match_operand:<VWIDE> 1 "register_operand" "w")
(ANY_EXTEND:<VWIDE>
- (match_operand:VDW 2 "register_operand" "w"))))]
+ (match_operand:VD_BHSI 2 "register_operand" "w"))))]
"TARGET_SIMD"
"<ANY_EXTEND:su><ADDSUB:optab>w\\t%0.<Vwtype>, %1.<Vwtype>, %2.<Vtype>"
[(set_attr "type" "neon_<ADDSUB:optab>_widen")]
@@ -2644,9 +2646,9 @@
;; <su><r>h<addsub>.
(define_insn "aarch64_<sur>h<addsub><mode>"
- [(set (match_operand:VQ_S 0 "register_operand" "=w")
- (unspec:VQ_S [(match_operand:VQ_S 1 "register_operand" "w")
- (match_operand:VQ_S 2 "register_operand" "w")]
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (unspec:VDQ_BHSI [(match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")]
HADDSUB))]
"TARGET_SIMD"
"<sur>h<addsub>\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
@@ -3660,7 +3662,7 @@
(define_insn "aarch64_<sur>shll_n<mode>"
[(set (match_operand:<VWIDE> 0 "register_operand" "=w")
- (unspec:<VWIDE> [(match_operand:VDW 1 "register_operand" "w")
+ (unspec:<VWIDE> [(match_operand:VD_BHSI 1 "register_operand" "w")
(match_operand:SI 2
"aarch64_simd_shift_imm_bitsize_<ve_mode>" "i")]
VSHLL))]
@@ -3774,8 +3776,8 @@
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w,w")
(neg:<V_cmp_result>
(COMPARISONS:<V_cmp_result>
- (match_operand:VDQ 1 "register_operand" "w,w")
- (match_operand:VDQ 2 "aarch64_simd_reg_or_zero" "w,ZDz")
+ (match_operand:VDQ_I 1 "register_operand" "w,w")
+ (match_operand:VDQ_I 2 "aarch64_simd_reg_or_zero" "w,ZDz")
)))]
"TARGET_SIMD"
"@
@@ -3839,8 +3841,8 @@
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
(neg:<V_cmp_result>
(UCOMPARISONS:<V_cmp_result>
- (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w")
+ (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w")
)))]
"TARGET_SIMD"
"cm<n_optab>\t%<v>0<Vmtype>, %<v><cmp_1><Vmtype>, %<v><cmp_2><Vmtype>"
@@ -3906,10 +3908,10 @@
[(set (match_operand:<V_cmp_result> 0 "register_operand" "=w")
(plus:<V_cmp_result>
(eq:<V_cmp_result>
- (and:VDQ
- (match_operand:VDQ 1 "register_operand" "w")
- (match_operand:VDQ 2 "register_operand" "w"))
- (match_operand:VDQ 3 "aarch64_simd_imm_zero"))
+ (and:VDQ_I
+ (match_operand:VDQ_I 1 "register_operand" "w")
+ (match_operand:VDQ_I 2 "register_operand" "w"))
+ (match_operand:VDQ_I 3 "aarch64_simd_imm_zero"))
(match_operand:<V_cmp_result> 4 "aarch64_simd_imm_minus_one")))
]
"TARGET_SIMD"
@@ -32,9 +32,6 @@
;; Iterator for all integer modes (up to 64-bit)
(define_mode_iterator ALLI [QI HI SI DI])
-;; Iterator scalar modes (up to 64-bit)
-(define_mode_iterator SDQ_I [QI HI SI DI])
-
;; Iterator for all integer modes that can be extended (up to 64-bit)
(define_mode_iterator ALLX [QI HI SI])
@@ -42,9 +39,6 @@
(define_mode_iterator GPF [SF DF])
;; Integer vector modes.
-(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
-
-;; Integer vector modes.
(define_mode_iterator VDQ_I [V8QI V16QI V4HI V8HI V2SI V4SI V2DI])
;; vector and scalar, 64 & 128-bit container, all integer modes
@@ -72,16 +66,6 @@
;; Quad vector with only 2 element modes.
(define_mode_iterator VQ_2E [V2DI V2DF])
-;; All vector modes, except double.
-(define_mode_iterator VQ_S [V8QI V16QI V4HI V8HI V2SI V4SI])
-
-;; Vector and scalar, 64 & 128-bit container: all vector integer mode;
-;; 8, 16, 32-bit scalar integer modes
-(define_mode_iterator VSDQ_I_BHSI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI QI HI SI])
-
-;; Vector modes for moves.
-(define_mode_iterator VDQM [V8QI V16QI V4HI V8HI V2SI V4SI])
-
;; This mode iterator allows :P to be used for patterns that operate on
;; addresses in different modes. In LP64, only DI will match, while in
;; ILP32, either can match.
@@ -132,9 +116,6 @@
;; All quad integer narrow-able modes.
(define_mode_iterator VQN [V8HI V4SI V2DI])
-;; All double integer widen-able modes.
-(define_mode_iterator VDW [V8QI V4HI V2SI])
-
;; Vector and scalar 128-bit container: narrowable 16, 32, 64-bit integer modes
(define_mode_iterator VSQN_HSDI [V8HI V4SI V2DI HI SI DI])
@@ -144,9 +125,6 @@
;; Double vector modes for combines.
(define_mode_iterator VDC [V8QI V4HI V2SI V2SF DI DF])
-;; Double vector modes for combines.
-(define_mode_iterator VDIC [V8QI V4HI V2SI])
-
;; Double vector modes inc V1DF
(define_mode_iterator VD1 [V8QI V4HI V2SI V2SF V1DF])
@@ -162,9 +140,6 @@
;; Vector modes for H, S and D types.
(define_mode_iterator VDQHSD [V4HI V8HI V2SI V4SI V2DI])
-;; Vector modes for Q, H and S types.
-(define_mode_iterator VDQQHS [V8QI V16QI V4HI V8HI V2SI V4SI])
-
;; Vector and scalar integer modes for H and S
(define_mode_iterator VSDQ_HSI [V4HI V8HI V2SI V4SI HI SI])
@@ -484,7 +459,7 @@
)
-;; Widened mode register suffixes for VDW/VQW.
+;; Widened mode register suffixes for VD_BHSI/VQW.
(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
(V2SI "2d") (V16QI "8h")
(V8HI "4s") (V4SI "2d")])