@@ -136,7 +136,6 @@ static enum aarch64_type_qualifiers
aarch64_types_unopu_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_unsigned, qualifier_unsigned };
#define TYPES_UNOPU (aarch64_types_unopu_qualifiers)
-#define TYPES_CREATE (aarch64_types_unop_qualifiers)
static enum aarch64_type_qualifiers
aarch64_types_binop_qualifiers[SIMD_MAX_BUILTIN_ARGS]
= { qualifier_none, qualifier_none, qualifier_maybe_immediate };
@@ -39,7 +39,6 @@
1-9 - CODE_FOR_<name><mode><1-9>
10 - CODE_FOR_<name><mode>. */
- BUILTIN_VD1 (CREATE, create, 0)
BUILTIN_VDC (COMBINE, combine, 0)
BUILTIN_VB (BINOP, pmul, 0)
BUILTIN_VDQF (UNOP, sqrt, 2)
@@ -2315,16 +2315,6 @@
;; Patterns for AArch64 SIMD Intrinsics.
-(define_expand "aarch64_create<mode>"
- [(match_operand:VD1 0 "register_operand" "")
- (match_operand:DI 1 "general_operand" "")]
- "TARGET_SIMD"
-{
- rtx src = gen_lowpart (<MODE>mode, operands[1]);
- emit_move_insn (operands[0], src);
- DONE;
-})
-
;; Lane extraction with sign extension to general purpose register.
(define_insn "*aarch64_get_lane_extend<GPI:mode><VDQQH:mode>"
[(set (match_operand:GPI 0 "register_operand" "=r")
@@ -2662,7 +2662,7 @@ vcreate_u64 (uint64_t __a)
__extension__ static __inline float64x1_t __attribute__ ((__always_inline__))
vcreate_f64 (uint64_t __a)
{
- return __builtin_aarch64_createv1df (__a);
+ return (float64x1_t) __a;
}
__extension__ static __inline poly8x8_t __attribute__ ((__always_inline__))
@@ -3262,7 +3262,7 @@ vreinterpret_f64_s32 (int32x2_t __a)
__extension__ static __inline float64x1_t __attribute__((__always_inline__))
vreinterpret_f64_s64 (int64x1_t __a)
{
- return __builtin_aarch64_createv1df ((uint64_t) vget_lane_s64 (__a, 0));
+ return (float64x1_t) __a;
}
__extension__ static __inline float64x1_t __attribute__((__always_inline__))
@@ -3286,7 +3286,7 @@ vreinterpret_f64_u32 (uint32x2_t __a)
__extension__ static __inline float64x1_t __attribute__((__always_inline__))
vreinterpret_f64_u64 (uint64x1_t __a)
{
- return __builtin_aarch64_createv1df (vget_lane_u64 (__a, 0));
+ return (float64x1_t) __a;
}
__extension__ static __inline float64x2_t __attribute__((__always_inline__))
@@ -147,9 +147,6 @@
;; Double vector modes for combines.
(define_mode_iterator VDIC [V8QI V4HI V2SI])
-;; Double vector modes inc V1DF
-(define_mode_iterator VD1 [V8QI V4HI V2SI V2SF V1DF])
-
;; Vector modes except double int.
(define_mode_iterator VDQIF [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DF])
@@ -7,6 +7,10 @@
#define EPS 1.0e-15
+#define INHIB_OPT(x) asm volatile ("mov %d0, %1.d[0]" \
+ : "=w"(x) \
+ : "w"(x) \
+ : /* No clobbers. */);
extern void abort (void);
@@ -24,6 +28,10 @@ main (void)
arg2 = vcreate_f64 (0x3fa88480812d6670ULL);
arg3 = vcreate_f64 (0x3fd5791ae2a92572ULL);
+ INHIB_OPT (arg1);
+ INHIB_OPT (arg2);
+ INHIB_OPT (arg3);
+
expected = 0.6280448184360076;
actual = vget_lane_f64 (vfma_f64 (arg1, arg2, arg3), 0);
@@ -7,6 +7,10 @@
#define EPS 1.0e-15
+#define INHIB_OPT(x) asm volatile ("mov %d0, %1.d[0]" \
+ : "=w"(x) \
+ : "w"(x) \
+ : /* No clobbers. */);
extern void abort (void);
@@ -24,6 +28,10 @@ main (void)
arg2 = vcreate_f64 (0x3fe6b78680fa29ceULL);
arg3 = vcreate_f64 (0x3feea3cbf921fbe0ULL);
+ INHIB_OPT (arg1);
+ INHIB_OPT (arg2);
+ INHIB_OPT (arg3);
+
expected = 4.4964705746355915e-2;
actual = vget_lane_f64 (vfms_f64 (arg1, arg2, arg3), 0);