Message ID | 1410949674-15633-1-git-send-email-Priyanka.Jain@freescale.com |
---|---|
State | Accepted |
Delegated to: | York Sun |
Headers | show |
On 09/17/2014 03:27 AM, Priyanka Jain wrote: > -A_007662 states that for x1 link width, PCIe2 controller trains in > Gen1 speed while configured for Gen2 speed. > Workaround:Set the width to x1 and speed to Gen2 by writing to > CCSR registers in PBI phase > > -A_008007 states that PVR register may show random value. > Workaround: Reset PVR register using DCSR space in PBI phase > > Add PBI based software workaround for A_007662 and A_008007 > in t104x_pbi.cfg. This is required for SPL-based bootloaders > like NAND-boot, SD-boot, SPI-boot > > Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> > --- Applied to u-boot-mpc85xx master. Thanks. York
diff --git a/board/freescale/t104xrdb/t104x_pbi.cfg b/board/freescale/t104xrdb/t104x_pbi.cfg index 7b9e9b0..b83b9b7 100644 --- a/board/freescale/t104xrdb/t104x_pbi.cfg +++ b/board/freescale/t104xrdb/t104x_pbi.cfg @@ -1,4 +1,14 @@ #PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 #Initialize CPC1 09010000 00200400 09138000 00000000
-A_007662 states that for x1 link width, PCIe2 controller trains in Gen1 speed while configured for Gen2 speed. Workaround:Set the width to x1 and speed to Gen2 by writing to CCSR registers in PBI phase -A_008007 states that PVR register may show random value. Workaround: Reset PVR register using DCSR space in PBI phase Add PBI based software workaround for A_007662 and A_008007 in t104x_pbi.cfg. This is required for SPL-based bootloaders like NAND-boot, SD-boot, SPI-boot Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> --- board/freescale/t104xrdb/t104x_pbi.cfg | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-)