| Message ID | 1413883364-681-3-git-send-email-sebastian.hesselbarth@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 21 October 2014 11:22, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> wrote: > commit bb8175a8aa42d731a840cd474e348ac3367eb5a0 > ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") > added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. > > While the differentation may be useful, pxav3 SDHCI controller lacks > a corresponding check in its custom .set_uhs_signaling callback for > MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 > to MMC_TIMING_UHS_DDR50 case. > > Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Thanks! Applied for next! Kind regards Uffe > --- > Cc: Chris Ball <chris@printf.net> > Cc: Ulf Hansson <ulf.hansson@linaro.org> > Cc: "Antoine Ténart" <antoine.tenart@free-electrons.com> > Cc: linux-mmc@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > drivers/mmc/host/sdhci-pxav3.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c > index 5036d7d39529..b55c807982fe 100644 > --- a/drivers/mmc/host/sdhci-pxav3.c > +++ b/drivers/mmc/host/sdhci-pxav3.c > @@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) > case MMC_TIMING_UHS_SDR104: > ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; > break; > + case MMC_TIMING_MMC_DDR52: > case MMC_TIMING_UHS_DDR50: > ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; > break; > -- > 2.1.1 >
diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index 5036d7d39529..b55c807982fe 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) case MMC_TIMING_UHS_SDR104: ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180; break; + case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180; break;
commit bb8175a8aa42d731a840cd474e348ac3367eb5a0 ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. While the differentation may be useful, pxav3 SDHCI controller lacks a corresponding check in its custom .set_uhs_signaling callback for MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 to MMC_TIMING_UHS_DDR50 case. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- Cc: Chris Ball <chris@printf.net> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: "Antoine Ténart" <antoine.tenart@free-electrons.com> Cc: linux-mmc@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/mmc/host/sdhci-pxav3.c | 1 + 1 file changed, 1 insertion(+)