| Message ID | 1403882530-47821-19-git-send-email-leon.alrae@imgtec.com |
|---|---|
| State | New |
| Headers | show |
There is a block of code that modifies CP0_Status_rw_bitmask.CP0St_FR
bit to read-writable in the same function.
So effectively in case of MIPS64 R6 the bit is now R/W which shouldn't be.
You need to modify or merge the code.
# if defined(TARGET_MIPS64)
/* For MIPS64, init FR bit to 1 if FPU unit is there and bit is
writable. */
if ((env->CP0_Config1 & (1 << CP0C1_FP)) &&
(env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) {
env->CP0_Status |= (1 << CP0St_FR);
}
# endif
Regards,
Yongbok
On 27/06/14 16:22, Leon Alrae wrote:
> Status.FR bit must be ignored on write and read as 1 when an implementation of
> Release 6 of the Architecture in which a 64-bit floating point unit is
> implemented.
>
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> ---
> v3:
> * remove line modifying CP0_Status_rw_bitmask as this is done while defining
> CPU
> ---
> target-mips/translate.c | 6 ++++++
> 1 files changed, 6 insertions(+), 0 deletions(-)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index a804322..7cfda3d 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -17942,6 +17942,12 @@ void cpu_state_reset(CPUMIPSState *env)
> }
> }
> #endif
> + if ((env->insn_flags & ISA_MIPS32R6) &&
> + (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
> + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
> + env->CP0_Status |= (1 << CP0St_FR);
> + }
> +
> compute_hflags(env);
> cs->exception_index = EXCP_NONE;
> }
Correction: it is not updating the bit but checking the bit. Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> On 02/10/14 11:21, Yongbok Kim wrote: > There is a block of code that modifies CP0_Status_rw_bitmask.CP0St_FR > bit to read-writable in the same function. > So effectively in case of MIPS64 R6 the bit is now R/W which shouldn't be. > You need to modify or merge the code. > > # if defined(TARGET_MIPS64) > /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is > writable. */ > if ((env->CP0_Config1 & (1 << CP0C1_FP)) && > (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { > env->CP0_Status |= (1 << CP0St_FR); > } > # endif > > Regards, > Yongbok > > > On 27/06/14 16:22, Leon Alrae wrote: >> Status.FR bit must be ignored on write and read as 1 when an implementation of >> Release 6 of the Architecture in which a 64-bit floating point unit is >> implemented. >> >> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> >> --- >> v3: >> * remove line modifying CP0_Status_rw_bitmask as this is done while defining >> CPU >> --- >> target-mips/translate.c | 6 ++++++ >> 1 files changed, 6 insertions(+), 0 deletions(-) >> >> diff --git a/target-mips/translate.c b/target-mips/translate.c >> index a804322..7cfda3d 100644 >> --- a/target-mips/translate.c >> +++ b/target-mips/translate.c >> @@ -17942,6 +17942,12 @@ void cpu_state_reset(CPUMIPSState *env) >> } >> } >> #endif >> + if ((env->insn_flags & ISA_MIPS32R6) && >> + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { >> + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ >> + env->CP0_Status |= (1 << CP0St_FR); >> + } >> + >> compute_hflags(env); >> cs->exception_index = EXCP_NONE; >> } >
diff --git a/target-mips/translate.c b/target-mips/translate.c index a804322..7cfda3d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -17942,6 +17942,12 @@ void cpu_state_reset(CPUMIPSState *env) } } #endif + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + } + compute_hflags(env); cs->exception_index = EXCP_NONE; }
Status.FR bit must be ignored on write and read as 1 when an implementation of Release 6 of the Architecture in which a 64-bit floating point unit is implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> --- v3: * remove line modifying CP0_Status_rw_bitmask as this is done while defining CPU --- target-mips/translate.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)