| Message ID | 1407477449-7447-1-git-send-email-tharvey@gateworks.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Stefano Babic |
| Headers | show |
On Friday, August 08, 2014 at 07:57:29 AM, Tim Harvey wrote: > According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable > for SS function) must remain deasserted until the reference clock is > running at the appropriate frequency. > > Without this patch we find a high link failure rate (>5%) on certain > IMX6 boards at various temperatures. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Marek Vasut <marex@denx.de> Best regards, Marek Vasut
Hi Tim, On Fri, Aug 8, 2014 at 2:57 AM, Tim Harvey <tharvey@gateworks.com> wrote: > According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable > for SS function) must remain deasserted until the reference clock is running > at the appropriate frequency. > > Without this patch we find a high link failure rate (>5%) on certain > IMX6 boards at various temperatures. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> Looks good, thanks. Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Also Cc Richard and Rogerio in case they have any comment. > --- > drivers/pci/pcie_imx.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c > index c48737e..a3982c4 100644 > --- a/drivers/pci/pcie_imx.c > +++ b/drivers/pci/pcie_imx.c > @@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void) > > imx6_pcie_toggle_power(); > > - /* Enable PCIe */ > - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); > - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); > - > enable_pcie_clock(); > > /* > @@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void) > */ > mdelay(50); > > + /* Enable PCIe */ > + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); > + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); > + > imx6_pcie_toggle_reset(); > > return 0;
On Friday, August 08, 2014 at 03:02:27 PM, Fabio Estevam wrote: > Hi Tim, > > On Fri, Aug 8, 2014 at 2:57 AM, Tim Harvey <tharvey@gateworks.com> wrote: > > According to the IMX6 reference manuals, REF_SSP_EN (Reference clock > > enable for SS function) must remain deasserted until the reference clock > > is running at the appropriate frequency. > > > > Without this patch we find a high link failure rate (>5%) on certain > > IMX6 boards at various temperatures. > > > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > > Looks good, thanks. > > Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> > > Also Cc Richard and Rogerio in case they have any comment. Can you guys test it on FSL hardware ? Best regards, Marek Vasut
Hi Tim, On 08/08/2014 07:57, Tim Harvey wrote: > According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable > for SS function) must remain deasserted until the reference clock is running > at the appropriate frequency. > > Without this patch we find a high link failure rate (>5%) on certain > IMX6 boards at various temperatures. > > Signed-off-by: Tim Harvey <tharvey@gateworks.com> > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c48737e..a3982c4 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -509,10 +509,6 @@ static int imx6_pcie_deassert_core_reset(void) imx6_pcie_toggle_power(); - /* Enable PCIe */ - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); - enable_pcie_clock(); /* @@ -521,6 +517,10 @@ static int imx6_pcie_deassert_core_reset(void) */ mdelay(50); + /* Enable PCIe */ + clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); + setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); + imx6_pcie_toggle_reset(); return 0;
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey <tharvey@gateworks.com> --- drivers/pci/pcie_imx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)