[v2,11/22] target-mips: Status.UX/SX/KX enable 32-bit address wrapping

In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
---
v2:
* set hflag indicating 32-bit wrapping in compute_hflags
---
 target-mips/cpu.h       |   18 ++++++++++++++----
 target-mips/translate.c |    6 +-----
 2 files changed, 15 insertions(+), 9 deletions(-)

On Wed, Jun 11, 2014 at 04:19:41PM +0100, Leon Alrae wrote:
> In R6 the special behaviour for data references is also specified for Kernel
> and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
> MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.
> 
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> ---
> v2:
> * set hflag indicating 32-bit wrapping in compute_hflags
> ---
>  target-mips/cpu.h       |   18 ++++++++++++++----
>  target-mips/translate.c |    6 +-----
>  2 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index a9b2c7a..85ff529 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -448,7 +448,7 @@ struct CPUMIPSState {
>         and RSQRT.D.  */
>  #define MIPS_HFLAG_COP1X  0x00080 /* COP1X instructions enabled         */
>  #define MIPS_HFLAG_RE     0x00100 /* Reversed endianness                */
> -#define MIPS_HFLAG_UX     0x00200 /* 64-bit user mode                   */
> +#define MIPS_HFLAG_AWRAP  0x00200 /* 32-bit compatibility address wrapping */
>  #define MIPS_HFLAG_M16    0x00400 /* MIPS16 mode flag                   */
>  #define MIPS_HFLAG_M16_SHIFT 10
>      /* If translation is interrupted between the branch instruction and
> @@ -722,7 +722,7 @@ static inline void compute_hflags(CPUMIPSState *env)
>  {
>      env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
>                       MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
> -                     MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
> +                     MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
>      if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
>          !(env->CP0_Status & (1 << CP0St_ERL)) &&
>          !(env->hflags & MIPS_HFLAG_DM)) {
> @@ -734,8 +734,18 @@ static inline void compute_hflags(CPUMIPSState *env)
>          (env->CP0_Status & (1 << CP0St_UX))) {
>          env->hflags |= MIPS_HFLAG_64;
>      }
> -    if (env->CP0_Status & (1 << CP0St_UX)) {
> -        env->hflags |= MIPS_HFLAG_UX;
> +
> +    if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
> +        !(env->CP0_Status & (1 << CP0St_UX))) {
> +        env->hflags |= MIPS_HFLAG_AWRAP;
> +    } else if (env->insn_flags & ISA_MIPS32R6) {
> +        /* Address wrapping for Supervisor and Kernel is specified in R6 */
> +        if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
> +             !(env->CP0_Status & (1 << CP0St_SX))) ||
> +            (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
> +             !(env->CP0_Status & (1 << CP0St_KX)))) {
> +            env->hflags |= MIPS_HFLAG_AWRAP;
> +        }
>      }
>  #endif
>      if ((env->CP0_Status & (1 << CP0St_CU0)) ||
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 8472fae..363b178 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -1379,11 +1379,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv
>      tcg_gen_add_tl(ret, arg0, arg1);
>  
>  #if defined(TARGET_MIPS64)
> -    /* For compatibility with 32-bit code, data reference in user mode
> -       with Status_UX = 0 should be casted to 32-bit and sign extended.
> -       See the MIPS64 PRA manual, section 4.10. */
> -    if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
> -        !(ctx->hflags & MIPS_HFLAG_UX)) {
> +    if (ctx->hflags & MIPS_HFLAG_AWRAP) {
>          tcg_gen_ext32s_i64(ret, ret);
>      }
>  #endif

Thanks for the changes (and the improvement of the existing code).

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>