Message ID | 538DA1BF.3090500@arm.com |
---|---|
State | New |
Headers | show |
On 3 June 2014 11:21, Alan Lawrence <alan.lawrence@arm.com> wrote: > Ok, this fixes it. We'll output an ext...#0, which is little more than a > MOV, > but that seems appropriate in the circumstance. > > Regression tested check-gcc and check-g++ on aarch64-none-elf and > aarch64_be-none-elf. > > Ok for trunk? ChangeLog ? /Marcus
gcc/ChangeLog: * config/aarch64/aarch64.c (aarch64_evpc_ext): Allow+handle location==0. ? --Alan Marcus Shawcroft wrote: > On 3 June 2014 11:21, Alan Lawrence <alan.lawrence@arm.com> wrote: >> Ok, this fixes it. We'll output an ext...#0, which is little more than a >> MOV, >> but that seems appropriate in the circumstance. >> >> Regression tested check-gcc and check-g++ on aarch64-none-elf and >> aarch64_be-none-elf. >> >> Ok for trunk? > > > ChangeLog ? > > /Marcus >
On 3 June 2014 12:19, Alan Lawrence <alan.lawrence@arm.com> wrote: > gcc/ChangeLog: > > * config/aarch64/aarch64.c (aarch64_evpc_ext): Allow+handle > location==0. > > ? Allow and handle location == 0. Otherwise OK /Marcus
Pushed as r211177. Thanks, Alan Marcus Shawcroft wrote: > On 3 June 2014 12:19, Alan Lawrence <alan.lawrence@arm.com> wrote: >> gcc/ChangeLog: >> >> * config/aarch64/aarch64.c (aarch64_evpc_ext): Allow+handle >> location==0. >> >> ? > > Allow and handle location == 0. > > Otherwise OK > /Marcus >
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 898323820201c6a7e52b0224fbeffa2b263b3e39..36173edb3a7cd6818a511ab5bb81557bb65fa287 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -8111,9 +8111,6 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d) return false; } - /* The mid-end handles masks that just return one of the input vectors. */ - gcc_assert (location != 0); - switch (d->vmode) { case V16QImode: gen = gen_aarch64_extv16qi; break; @@ -8134,7 +8131,10 @@ aarch64_evpc_ext (struct expand_vec_perm_d *d) if (d->testing_p) return true; - if (BYTES_BIG_ENDIAN) + /* The case where (location == 0) is a no-op for both big- and little-endian, + and is removed by the mid-end at optimization levels -O1 and higher. */ + + if (BYTES_BIG_ENDIAN && (location != 0)) { /* After setup, we want the high elements of the first vector (stored at the LSB end of the register), and the low elements of the second