new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x8_t
+test_vrev16p8 (poly8x8_t _arg)
+{
+ return vrev16_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ poly8x8_t reversed = test_vrev16p8 (inorder);
+ poly8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev16_p8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16p8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x16_t
+test_vrev16qp8 (poly8x16_t _arg)
+{
+ return vrev16q_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ poly8x16_t reversed = test_vrev16qp8 (inorder);
+ poly8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev16q_p8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16qp8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x16_t
+test_vrev16qs8 (int8x16_t _arg)
+{
+ return vrev16q_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ int8x16_t reversed = test_vrev16qs8 (inorder);
+ int8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev16q_s8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16qs8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x16_t
+test_vrev16qu8 (uint8x16_t _arg)
+{
+ return vrev16q_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ uint8x16_t reversed = test_vrev16qu8 (inorder);
+ uint8x16_t expected = {2, 1, 4, 3, 6, 5, 8, 7, 10, 9, 12, 11, 14, 13, 16, 15};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev16q_u8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16qu8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x8_t
+test_vrev16s8 (int8x8_t _arg)
+{
+ return vrev16_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ int8x8_t reversed = test_vrev16s8 (inorder);
+ int8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev16_s8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16s8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x8_t
+test_vrev16u8 (uint8x8_t _arg)
+{
+ return vrev16_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ uint8x8_t reversed = test_vrev16u8 (inorder);
+ uint8x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev16_u8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev16u8.x"
+
+/* { dg-final { scan-assembler-times "rev16\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x4_t
+test_vrev32p16 (poly16x4_t _arg)
+{
+ return vrev32_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly16x4_t inorder = {1, 2, 3, 4};
+ poly16x4_t reversed = test_vrev32p16 (inorder);
+ poly16x4_t expected = {2, 1, 4, 3};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32_p16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32p16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x8_t
+test_vrev32p8 (poly8x8_t _arg)
+{
+ return vrev32_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ poly8x8_t reversed = test_vrev32p8 (inorder);
+ poly8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32_p8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32p8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x8_t
+test_vrev32qp16 (poly16x8_t _arg)
+{
+ return vrev32q_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ poly16x8_t reversed = test_vrev32qp16 (inorder);
+ poly16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_p16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qp16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x16_t
+test_vrev32qp8 (poly8x16_t _arg)
+{
+ return vrev32q_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ poly8x16_t reversed = test_vrev32qp8 (inorder);
+ poly8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_p8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qp8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x8_t
+test_vrev32qs16 (int16x8_t _arg)
+{
+ return vrev32q_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ int16x8_t reversed = test_vrev32qs16 (inorder);
+ int16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_s16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qs16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x16_t
+test_vrev32qs8 (int8x16_t _arg)
+{
+ return vrev32q_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ int8x16_t reversed = test_vrev32qs8 (inorder);
+ int8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_s8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qs8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x8_t
+test_vrev32qu16 (uint16x8_t _arg)
+{
+ return vrev32q_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ uint16x8_t reversed = test_vrev32qu16 (inorder);
+ uint16x8_t expected = {2, 1, 4, 3, 6, 5, 8, 7};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_u16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qu16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x16_t
+test_vrev32qu8 (uint8x16_t _arg)
+{
+ return vrev32q_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ uint8x16_t reversed = test_vrev32qu8 (inorder);
+ uint8x16_t expected = {4, 3, 2, 1, 8, 7, 6, 5, 12, 11, 10, 9, 16, 15, 14, 13};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32q_u8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32qu8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x4_t
+test_vrev32s16 (int16x4_t _arg)
+{
+ return vrev32_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int16x4_t inorder = {1, 2, 3, 4};
+ int16x4_t reversed = test_vrev32s16 (inorder);
+ int16x4_t expected = {2, 1, 4, 3};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32_s16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32s16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x8_t
+test_vrev32s8 (int8x8_t _arg)
+{
+ return vrev32_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ int8x8_t reversed = test_vrev32s8 (inorder);
+ int8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32_s8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32s8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x4_t
+test_vrev32u16 (uint16x4_t _arg)
+{
+ return vrev32_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint16x4_t inorder = {1, 2, 3, 4};
+ uint16x4_t reversed = test_vrev32u16 (inorder);
+ uint16x4_t expected = {2, 1, 4, 3};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32_u16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32u16.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x8_t
+test_vrev32u8 (uint8x8_t _arg)
+{
+ return vrev32_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ uint8x8_t reversed = test_vrev32u8 (inorder);
+ uint8x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev32_u8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev32u8.x"
+
+/* { dg-final { scan-assembler-times "rev32\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+float32x2_t
+test_vrev64f32 (float32x2_t _arg)
+{
+ return vrev64_f32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ float32x2_t inorder = {1, 2};
+ float32x2_t reversed = test_vrev64f32 (inorder);
+ float32x2_t expected = {2, 1};
+
+ for (i = 0; i < 2; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_f32' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64f32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x4_t
+test_vrev64p16 (poly16x4_t _arg)
+{
+ return vrev64_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly16x4_t inorder = {1, 2, 3, 4};
+ poly16x4_t reversed = test_vrev64p16 (inorder);
+ poly16x4_t expected = {4, 3, 2, 1};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_p16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64p16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x8_t
+test_vrev64p8 (poly8x8_t _arg)
+{
+ return vrev64_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ poly8x8_t reversed = test_vrev64p8 (inorder);
+ poly8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_p8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64p8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+float32x4_t
+test_vrev64qf32 (float32x4_t _arg)
+{
+ return vrev64q_f32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ float32x4_t inorder = {1, 2, 3, 4};
+ float32x4_t reversed = test_vrev64qf32 (inorder);
+ float32x4_t expected = {2, 1, 4, 3};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_f32' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qf32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly16x8_t
+test_vrev64qp16 (poly16x8_t _arg)
+{
+ return vrev64q_p16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ poly16x8_t reversed = test_vrev64qp16 (inorder);
+ poly16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_p16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qp16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+poly8x16_t
+test_vrev64qp8 (poly8x16_t _arg)
+{
+ return vrev64q_p8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ poly8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ poly8x16_t reversed = test_vrev64qp8 (inorder);
+ poly8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_p8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qp8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x8_t
+test_vrev64qs16 (int16x8_t _arg)
+{
+ return vrev64q_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ int16x8_t reversed = test_vrev64qs16 (inorder);
+ int16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_s16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qs16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int32x4_t
+test_vrev64qs32 (int32x4_t _arg)
+{
+ return vrev64q_s32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int32x4_t inorder = {1, 2, 3, 4};
+ int32x4_t reversed = test_vrev64qs32 (inorder);
+ int32x4_t expected = {2, 1, 4, 3};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_s32' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qs32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x16_t
+test_vrev64qs8 (int8x16_t _arg)
+{
+ return vrev64q_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ int8x16_t reversed = test_vrev64qs8 (inorder);
+ int8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_s8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qs8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x8_t
+test_vrev64qu16 (uint16x8_t _arg)
+{
+ return vrev64q_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint16x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ uint16x8_t reversed = test_vrev64qu16 (inorder);
+ uint16x8_t expected = {4, 3, 2, 1, 8, 7, 6, 5};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_u16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qu16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8h, ?v\[0-9\]+.8h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint32x4_t
+test_vrev64qu32 (uint32x4_t _arg)
+{
+ return vrev64q_u32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint32x4_t inorder = {1, 2, 3, 4};
+ uint32x4_t reversed = test_vrev64qu32 (inorder);
+ uint32x4_t expected = {2, 1, 4, 3};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_u32' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qu32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4s, ?v\[0-9\]+.4s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x16_t
+test_vrev64qu8 (uint8x16_t _arg)
+{
+ return vrev64q_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint8x16_t inorder = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
+ uint8x16_t reversed = test_vrev64qu8 (inorder);
+ uint8x16_t expected = {8, 7, 6, 5, 4, 3, 2, 1, 16, 15, 14, 13, 12, 11, 10, 9};
+
+ for (i = 0; i < 16; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64q_u8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64qu8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.16b, ?v\[0-9\]+.16b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int16x4_t
+test_vrev64s16 (int16x4_t _arg)
+{
+ return vrev64_s16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int16x4_t inorder = {1, 2, 3, 4};
+ int16x4_t reversed = test_vrev64s16 (inorder);
+ int16x4_t expected = {4, 3, 2, 1};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_s16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64s16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int32x2_t
+test_vrev64s32 (int32x2_t _arg)
+{
+ return vrev64_s32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int32x2_t inorder = {1, 2};
+ int32x2_t reversed = test_vrev64s32 (inorder);
+ int32x2_t expected = {2, 1};
+
+ for (i = 0; i < 2; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_s32' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64s32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+int8x8_t
+test_vrev64s8 (int8x8_t _arg)
+{
+ return vrev64_s8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ int8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ int8x8_t reversed = test_vrev64s8 (inorder);
+ int8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_s8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64s8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint16x4_t
+test_vrev64u16 (uint16x4_t _arg)
+{
+ return vrev64_u16 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint16x4_t inorder = {1, 2, 3, 4};
+ uint16x4_t reversed = test_vrev64u16 (inorder);
+ uint16x4_t expected = {4, 3, 2, 1};
+
+ for (i = 0; i < 4; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_u16' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64u16.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.4h, ?v\[0-9\]+.4h!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint32x2_t
+test_vrev64u32 (uint32x2_t _arg)
+{
+ return vrev64_u32 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint32x2_t inorder = {1, 2};
+ uint32x2_t reversed = test_vrev64u32 (inorder);
+ uint32x2_t expected = {2, 1};
+
+ for (i = 0; i < 2; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_u32' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64u32.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.2s, ?v\[0-9\]+.2s!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
new file mode 100644
@@ -0,0 +1,22 @@
+extern void abort (void);
+
+uint8x8_t
+test_vrev64u8 (uint8x8_t _arg)
+{
+ return vrev64_u8 (_arg);
+}
+
+int
+main (int argc, char **argv)
+{
+ int i;
+ uint8x8_t inorder = {1, 2, 3, 4, 5, 6, 7, 8};
+ uint8x8_t reversed = test_vrev64u8 (inorder);
+ uint8x8_t expected = {8, 7, 6, 5, 4, 3, 2, 1};
+
+ for (i = 0; i < 8; i++)
+ if (reversed[i] != expected[i])
+ abort ();
+ return 0;
+}
+
new file mode 100644
@@ -0,0 +1,10 @@
+/* Test the `vrev64_u8' AArch64 SIMD intrinsic. */
+
+/* { dg-do run } */
+/* { dg-options "-save-temps -fno-inline" } */
+
+#include <arm_neon.h>
+#include "vrev64u8.x"
+
+/* { dg-final { scan-assembler-times "rev64\[ \t\]+v\[0-9\]+.8b, ?v\[0-9\]+.8b!?\(?:\[ \t\]+@\[a-zA-Z0-9 \]+\)?\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */