| Message ID | 530F446D.2020007@arm.com |
|---|---|
| State | New |
| Headers | show |
On 27 February 2014 14:58, Ramana Radhakrishnan <ramrad01@arm.com> wrote: > Hi > > I noticed that for T32 we don't allow any old register for DImode values. > The restriction of an even register is true only for ARM state because the > ISA doesn't allow any old register in this place. In a few large .i files > that I had knocking about, noticed a nice drop in stack usage and a > generally improved register allocation strategy. > > Queued for stage1 after suitable testing including a bootstrap and > regression test in Thumb2 found no issues. > > regards > Ramana > > <DATE> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> > > * config/arm/arm.c (arm_hard_regno_mode_ok): Loosen restrictions on > core registers for DImode values in Thumb2. > Hi Ramana, I've noticed some regressions after this patch has been committed (rev 209615): gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer -funroll-all-loops -finline-functions gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer -funroll-loops gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto -fno-use-linker-plugin -flto-partition=none gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects Now all produce ICE in several GCC configurations (mostly when generating thumb code) eg: --target arm-none-eabi --with-cpu=cortex-a9 --with-mode=thumb --target arm-none-linux-gnueabi --with-cpu=cortex-a9 --with-mode=thumb but it's OK for target arm-none-linux-gnueabihf. See http://cbuild.validation.linaro.org/build/cross-validation/gcc/209615/report-build-info.html Christophe.
On Wed, Apr 23, 2014 at 1:53 PM, Christophe Lyon <christophe.lyon@linaro.org> wrote: > On 27 February 2014 14:58, Ramana Radhakrishnan <ramrad01@arm.com> wrote: >> Hi >> >> I noticed that for T32 we don't allow any old register for DImode values. >> The restriction of an even register is true only for ARM state because the >> ISA doesn't allow any old register in this place. In a few large .i files >> that I had knocking about, noticed a nice drop in stack usage and a >> generally improved register allocation strategy. >> >> Queued for stage1 after suitable testing including a bootstrap and >> regression test in Thumb2 found no issues. >> >> regards >> Ramana >> >> <DATE> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> >> >> * config/arm/arm.c (arm_hard_regno_mode_ok): Loosen restrictions on >> core registers for DImode values in Thumb2. >> > > Hi Ramana, > > I've noticed some regressions after this patch has been committed (rev 209615): > > gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer > -funroll-all-loops -finline-functions > gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer -funroll-loops > gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 > gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto > -fno-use-linker-plugin -flto-partition=none > gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto > -fuse-linker-plugin -fno-fat-lto-objects > Now all produce ICE in several GCC configurations (mostly when > generating thumb code) eg: > --target arm-none-eabi --with-cpu=cortex-a9 --with-mode=thumb > --target arm-none-linux-gnueabi --with-cpu=cortex-a9 --with-mode=thumb > Thanks for the report - I'll have a look. I've had this in a tree for testing for sometime that runs these configurations atleast the bare-metal arm-none-eabi one with multilib testing for thumb. > but it's OK for target arm-none-linux-gnueabihf. > > See http://cbuild.validation.linaro.org/build/cross-validation/gcc/209615/report-build-info.html > > Christophe.
On Wed, Apr 23, 2014 at 2:06 PM, Ramana Radhakrishnan <ramana.gcc@googlemail.com> wrote: > On Wed, Apr 23, 2014 at 1:53 PM, Christophe Lyon > <christophe.lyon@linaro.org> wrote: >> On 27 February 2014 14:58, Ramana Radhakrishnan <ramrad01@arm.com> wrote: >>> Hi >>> >>> I noticed that for T32 we don't allow any old register for DImode values. >>> The restriction of an even register is true only for ARM state because the >>> ISA doesn't allow any old register in this place. In a few large .i files >>> that I had knocking about, noticed a nice drop in stack usage and a >>> generally improved register allocation strategy. >>> >>> Queued for stage1 after suitable testing including a bootstrap and >>> regression test in Thumb2 found no issues. >>> >>> regards >>> Ramana >>> >>> <DATE> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> >>> >>> * config/arm/arm.c (arm_hard_regno_mode_ok): Loosen restrictions on >>> core registers for DImode values in Thumb2. >>> >> >> Hi Ramana, >> >> I've noticed some regressions after this patch has been committed (rev 209615): >> >> gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer >> -funroll-all-loops -finline-functions >> gcc.c-torture/compile/pr34856.c -O3 -fomit-frame-pointer -funroll-loops >> gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 >> gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto >> -fno-use-linker-plugin -flto-partition=none >> gcc.c-torture/execute/scal-to-vec1.c compilation, -O2 -flto >> -fuse-linker-plugin -fno-fat-lto-objects > > >> Now all produce ICE in several GCC configurations (mostly when >> generating thumb code) eg: >> --target arm-none-eabi --with-cpu=cortex-a9 --with-mode=thumb >> --target arm-none-linux-gnueabi --with-cpu=cortex-a9 --with-mode=thumb >> > > Thanks for the report - I'll have a look. I've had this in a tree for > testing for sometime that runs these configurations atleast the > bare-metal arm-none-eabi one with multilib testing for thumb. Uggh I hate it that gmail sometimes cuts off your sentences. "Needless to say, this is surprising" > >> but it's OK for target arm-none-linux-gnueabihf. >> >> See http://cbuild.validation.linaro.org/build/cross-validation/gcc/209615/report-build-info.html >> >> Christophe.
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index b49f43e..73dc04a 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -22593,12 +22593,19 @@ arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) } /* We allow almost any value to be stored in the general registers. - Restrict doubleword quantities to even register pairs so that we can - use ldrd. Do not allow very large Neon structure opaque modes in - general registers; they would use too many. */ + Restrict doubleword quantities to even register pairs in ARM state + so that we can use ldrd. Do not allow very large Neon structure + opaque modes in general registers; they would use too many. */ if (regno <= LAST_ARM_REGNUM) - return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0) - && ARM_NUM_REGS (mode) <= 4; + { + if (ARM_NUM_REGS (mode) > 4) + return FALSE; + + if (TARGET_THUMB2) + return TRUE; + + return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); + } if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
Hi I noticed that for T32 we don't allow any old register for DImode values. The restriction of an even register is true only for ARM state because the ISA doesn't allow any old register in this place. In a few large .i files that I had knocking about, noticed a nice drop in stack usage and a generally improved register allocation strategy. Queued for stage1 after suitable testing including a bootstrap and regression test in Thumb2 found no issues. regards Ramana <DATE> Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> * config/arm/arm.c (arm_hard_regno_mode_ok): Loosen restrictions on core registers for DImode values in Thumb2.