Message ID | 523B03A0.5080005@st.com |
---|---|
State | New |
Headers | show |
Christian Bruel <christian.bruel@st.com> wrote: > This patch fixes the aforementioned PR by refusing FPUL_REG to be an > acceptable reg for any arithmetic_operand on TARGET_SH4. (This was a > strange SH4 singularity with regards to the SH family). > > The only impacted insn is movsf_ie used for reg-fpreg transfers. So the > condition now mentions explicitly fpul_operand, allowing to simplify a > bit the logic to match by removing the extra checks. > > The testsuite survived (no regression) for > -m2,-m2a,-m2a-nofpu,-m2a-single,-m2a-single-only,-m3,-m3e,-m4,-m4-single,-m4-single-only,-m4a,-m4a-single,-m4a-single-only > > No performance impact on a large number of benchmarks (CSIBE, EEMBC, > Coremark, ...) > > sh4-linux-elf survived a full Linux distribution rebuild > > OK for trunk? OK. Regards, kaz
Christian Bruel <christian.bruel@st.com> wrote: > (define_insn "*mov<mode>_reg_reg" > - [(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z") > - (match_operand:QIHI 1 "register_operand" "r,*z,m"))] > - "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)" > + [(set (match_operand:QIHI 0 "general_movdst_operand" "=r,m,*z") > + (match_operand:QIHI 1 "general_movsrc_operand" "r,*z,m"))] > + "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode) > + && arith_reg_dest (operands[0], <MODE>mode) > + && register_operand (operands[1], <MODE>mode)" I thought that predicates explicitly allowing mem only when reload in progress are defensive because I guess there is no guarantee that the condition part of the insn will be never used in spilling. Re-factoring suggested by Oleg and Rechard would be the right thing to do, though it might be a bit invasive for 4.8. Regards, kaz
> Christian Bruel <christian.bruel@st.com> wrote: >> (define_insn "*mov<mode>_reg_reg" >> - [(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z") >> - (match_operand:QIHI 1 "register_operand" "r,*z,m"))] >> - "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)" >> + [(set (match_operand:QIHI 0 "general_movdst_operand" "=r,m,*z") >> + (match_operand:QIHI 1 "general_movsrc_operand" "r,*z,m"))] >> + "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode) >> + && arith_reg_dest (operands[0], <MODE>mode) >> + && register_operand (operands[1], <MODE>mode)" > > I thought that predicates explicitly allowing mem only when reload > in progress are defensive because I guess there is no guarantee > that the condition part of the insn will be never used in spilling. > Re-factoring suggested by Oleg and Rechard would be the right thing > to do, though it might be a bit invasive for 4.8. Ugh, this should be for Re: [PATCH, committed] SH: Fix PR58314 (unsatisfied constraints) http://gcc.gnu.org/ml/gcc-patches/2013-09/msg01447.html Sorry for wrong reply. Regards, kaz
On 09/20/2013 01:07 AM, Kaz Kojima wrote: > Christian Bruel <christian.bruel@st.com> wrote: >> This patch fixes the aforementioned PR by refusing FPUL_REG to be an >> acceptable reg for any arithmetic_operand on TARGET_SH4. (This was a >> strange SH4 singularity with regards to the SH family). >> >> The only impacted insn is movsf_ie used for reg-fpreg transfers. So the >> condition now mentions explicitly fpul_operand, allowing to simplify a >> bit the logic to match by removing the extra checks. >> >> The testsuite survived (no regression) for >> -m2,-m2a,-m2a-nofpu,-m2a-single,-m2a-single-only,-m3,-m3e,-m4,-m4-single,-m4-single-only,-m4a,-m4a-single,-m4a-single-only >> >> No performance impact on a large number of benchmarks (CSIBE, EEMBC, >> Coremark, ...) >> >> sh4-linux-elf survived a full Linux distribution rebuild >> >> OK for trunk? > OK. > > Regards, > kaz committed. Note that this fixes the ICE: testsuite/gcc.c-torture/compile/pr55921.c:21:1: error: insn does not satisfy its constraints: (insn 128 33 129 (parallel [ (set (reg:SF 65 fr1 [ cf ]) (reg:SF 3 r3)) (use (reg/v:PSI 151 )) (clobber (scratch:SI)) ]) for -m2a (but still fails with error: 'asm' operand requires impossible reload as previously with the other configurations) Thanks Christian
2013-09-19 Christian Bruel <christian.bruel@st.com> PR target/58475 * config/sh/sh.md (movsf_ie): Allow fpul_operand. * config/sh/predicate.md (arith_reg_operand): Disallow FPUL_REG. 2013-09-19 Christian Bruel <christian.bruel@st.com> PR target/58475 * gcc.target/sh/torture/pr58475.c: New test. Index: gcc/config/sh/predicates.md =================================================================== --- gcc/config/sh/predicates.md (revision 202699) +++ gcc/config/sh/predicates.md (working copy) @@ -154,7 +154,7 @@ return (regno != T_REG && regno != PR_REG && ! TARGET_REGISTER_P (regno) - && (regno != FPUL_REG || TARGET_SH4) + && regno != FPUL_REG && regno != MACH_REG && regno != MACL_REG); } /* Allow a no-op sign extension - compare LOAD_EXTEND_OP. Index: gcc/config/sh/sh.md =================================================================== --- gcc/config/sh/sh.md (revision 202699) +++ gcc/config/sh/sh.md (working copy) @@ -8203,15 +8205,9 @@ label: (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c")) (clobber (match_scratch:SI 3 "=X,X,Bsc,Bsc,&z,X,X,X,X,X,X,X,X,y,X,X,X,X,X"))] "TARGET_SH2E - && (arith_reg_operand (operands[0], SFmode) - || arith_reg_operand (operands[1], SFmode) - || arith_reg_operand (operands[3], SImode) - || (fpul_operand (operands[0], SFmode) - && memory_operand (operands[1], SFmode) - && GET_CODE (XEXP (operands[1], 0)) == POST_INC) - || (fpul_operand (operands[1], SFmode) - && memory_operand (operands[0], SFmode) - && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))" + && (arith_reg_operand (operands[0], SFmode) || fpul_operand (operands[0], SFmode) + || arith_reg_operand (operands[1], SFmode) || fpul_operand (operands[1], SFmode) + || arith_reg_operand (operands[3], SImode))" "@ fmov %1,%0 mov %1,%0 Index: gcc/testsuite/gcc.target/sh/torture/pr58475.c =================================================================== --- gcc/testsuite/gcc.target/sh/torture/pr58475.c (revision 0) +++ gcc/testsuite/gcc.target/sh/torture/pr58475.c (working copy) @@ -0,0 +1,15 @@ +/* { dg-do compile { target "sh*-*-*" } } */ + +int +kerninfo(int __bsx, double tscale) +{ + return ( + (int)(__extension__ + ({ + ((((__bsx) & 0xff000000u) >> 24) + | (((__bsx) & 0x00ff0000) >> 8) + | (((__bsx) & 0x0000ff00) << 8) + | (((__bsx) & 0x000000ff) << 24) + ); })) + * tscale); +}