diff mbox

[2/7] s390: Only use lhs zero_extract in word_mode

Message ID 1344565921-27852-3-git-send-email-rth@redhat.com
State New
Headers show

Commit Message

Richard Henderson Aug. 10, 2012, 2:31 a.m. UTC 
This means that anything targeting extimm or z10 must therefore
imply zarch, which implies word_mode == DImode.

Then, now that *insv_z10 is no longer dependent on mode, let gas
do some arithmetic, rather than doing it in C and generating new rtl.
---
 gcc/config/s390/s390.md |   45 ++++++++++++++++-----------------------------
 1 files changed, 16 insertions(+), 29 deletions(-)

Comments

Andreas Krebbel Nov. 6, 2012, 1 p.m. UTC | #1 
Hi,

I had to remove the insv pattern changes from that patch.  I
understand that you simplified the patterns since the generic RTL
expander only generates word mode zero extracts. However, we still
need the SImode variant for atomic operations so we cannot remove it.

The insv_z10 definition can still be simplified after adding the
bitsize mode attribute with one of your later patches so that change
will be moved to a later patch.

No regressions with that patch on s390x with -march=z196.

Feel free to apply.

Thanks!

Bye,

-Andreas-


 gcc/config/s390/s390.md |   17 !!!!!!!!!!!!!!!!!
 1 file changed, 17 modifications(!)

Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 3525,3539 ****
    [(set_attr "op_type" "RIL")
     (set_attr "z10prop" "z10_fwd_E1")])
  
! ; Update the right-most 32 bit of a DI, or the whole of a SI.
! (define_insn "*insv_l<mode>_reg_extimm"
!   [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
! 			(const_int 32)
! 			(match_operand 1 "const_int_operand" "n"))
! 	(match_operand:P 2 "const_int_operand" "n"))]
!   "TARGET_EXTIMM
!    && BITS_PER_WORD - INTVAL (operands[1]) == 32"
!   "iilf\t%0,%o2"
    [(set_attr "op_type" "RIL")
     (set_attr "z10prop" "z10_fwd_A1")])
  
--- 3525,3538 ----
    [(set_attr "op_type" "RIL")
     (set_attr "z10prop" "z10_fwd_E1")])
  
! ; Update the right-most 32 bit of a DI.
! (define_insn "*insv_l_di_reg_extimm"
!   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
! 			 (const_int 32)
! 			 (const_int 32))
! 	(match_operand:DI 1 "const_int_operand" "n"))]
!   "TARGET_EXTIMM"
!   "iilf\t%0,%o1"
    [(set_attr "op_type" "RIL")
     (set_attr "z10prop" "z10_fwd_A1")])
diff mbox

Patch

diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 76ec9c4..2677fb2 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3364,27 +3364,15 @@ 
   FAIL;
 })
 
-(define_insn "*insv<mode>_z10"
-  [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d")
-			  (match_operand 1 "const_int_operand"    "I")
-			  (match_operand 2 "const_int_operand"    "I"))
-	(match_operand:GPR 3 "nonimmediate_operand" "d"))
+(define_insn "*insv_z10"
+  [(set (zero_extract:DI
+	  (match_operand:DI 0 "nonimmediate_operand" "+d")
+	  (match_operand 1 "const_int_operand" "")
+	  (match_operand 2 "const_int_operand" ""))
+	(match_operand:DI 3 "nonimmediate_operand" "d"))
    (clobber (reg:CC CC_REGNUM))]
-  "TARGET_Z10
-   && (INTVAL (operands[1]) + INTVAL (operands[2])) <=
-      GET_MODE_BITSIZE (<MODE>mode)"
-{
-  int start = INTVAL (operands[2]);
-  int size = INTVAL (operands[1]);
-  int offset = 64 - GET_MODE_BITSIZE (<MODE>mode);
-
-  operands[2] = GEN_INT (offset + start);              /* start bit position */
-  operands[1] = GEN_INT (offset + start + size - 1);   /* end bit position */
-  operands[4] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) -
-			 start - size);       /* left shift count */
-
-  return "risbg\t%0,%3,%b2,%b1,%b4";
-}
+  "TARGET_Z10"
+  "risbg\t%0,%3,%2,%2+%1-1,64-%2-%1"
   [(set_attr "op_type" "RIE")
    (set_attr "z10prop" "z10_super_E1")])
 
@@ -3483,15 +3471,14 @@ 
   [(set_attr "op_type" "RIL")
    (set_attr "z10prop" "z10_fwd_E1")])
 
-; Update the right-most 32 bit of a DI, or the whole of a SI.
-(define_insn "*insv_l<mode>_reg_extimm"
-  [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d")
-			(const_int 32)
-			(match_operand 1 "const_int_operand" "n"))
-	(match_operand:P 2 "const_int_operand" "n"))]
-  "TARGET_EXTIMM
-   && BITS_PER_WORD - INTVAL (operands[1]) == 32"
-  "iilf\t%0,%o2"
+; Update the right-most 32 bit of a DI.
+(define_insn "*insv_l_di_reg_extimm"
+  [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d")
+			 (const_int 32)
+			 (const_int 32))
+	(match_operand:DI 1 "const_int_operand" "n"))]
+  "TARGET_EXTIMM"
+  "iilf\t%0,%o1"
   [(set_attr "op_type" "RIL")
    (set_attr "z10prop" "z10_fwd_A1")])