Message ID | 176388006.2143625.1344434132868.JavaMail.root@advansee.com |
---|---|
State | Awaiting Upstream |
Delegated to: | Stefano Babic |
Headers | show |
On 08/08/2012 15:55, Benoît Thébaudeau wrote: > The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W > cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using > the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) > resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. > > This patch fixes this issue by setting the NFC clock to the highest frequency > complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > Cc: John Rigby <jcrigby@gmail.com> > Cc: Scott Wood <scottwood@freescale.com> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Daniel Gachet <Daniel.Gachet@hefr.ch> > --- > This patch is a replacement solution that I suggest instead of > http://patchwork.ozlabs.org/patch/174735/ since there is no need for a > CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES config option in the NFC driver. > > It still has to be tested by someone having this board, but I'm very confident > that it works since I have another PCB design based on the i.MX25 with a NAND > Flash with the same timings that works fine using these clock settings. > > .../board/karo/tx25/lowlevel_init.S | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git u-boot-2012.07.orig/board/karo/tx25/lowlevel_init.S u-boot-2012.07/board/karo/tx25/lowlevel_init.S > index 823df10..eb3f187 100644 > --- u-boot-2012.07.orig/board/karo/tx25/lowlevel_init.S > +++ u-boot-2012.07/board/karo/tx25/lowlevel_init.S > @@ -67,6 +67,14 @@ > write32 0x53f80008, 0x20034000 > > /* > + * PCDR2: NFC = 33.25 MHz > + * This is required for the NAND Flash of this board, which is a Samsung > + * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with > + * the NFC driver in symmetric (i.e. one-cycle) mode. > + */ > + write32 0x53f80020, 0x01010103 > + > + /* This is a very local change, only for the Karo-TX25. I see no problem with it. Acked-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic
On 08/08/2012 15:55, Benoît Thébaudeau wrote: > The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W > cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using > the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) > resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. > > This patch fixes this issue by setting the NFC clock to the highest frequency > complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. > Applied to u-boot-imx(fix), thanks. Best regards, Stefano Babic
diff --git u-boot-2012.07.orig/board/karo/tx25/lowlevel_init.S u-boot-2012.07/board/karo/tx25/lowlevel_init.S index 823df10..eb3f187 100644 --- u-boot-2012.07.orig/board/karo/tx25/lowlevel_init.S +++ u-boot-2012.07/board/karo/tx25/lowlevel_init.S @@ -67,6 +67,14 @@ write32 0x53f80008, 0x20034000 /* + * PCDR2: NFC = 33.25 MHz + * This is required for the NAND Flash of this board, which is a Samsung + * K9F1G08U0B with 25-ns R/W cycle times, in order to make it work with + * the NFC driver in symmetric (i.e. one-cycle) mode. + */ + write32 0x53f80020, 0x01010103 + + /* * enable all implemented clocks in all three * clock control registers */
The NAND Flash of the KARO TX25 board is a Samsung K9F1G08U0B with 25-ns R/W cycle times. However, the NFC clock for this board was set to 66.5 MHz, so using the NFC driver in symmetric mode (i.e. 1 NFC clock cycle = 1 NF R/W cycle) resulted in NF R/W cycle times of 15 ns, hence corrupted NF accesses. This patch fixes this issue by setting the NFC clock to the highest frequency complying to the 25-ns NF R/W cycle times specification, i.e. 33.25 MHz. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: John Rigby <jcrigby@gmail.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Daniel Gachet <Daniel.Gachet@hefr.ch> --- This patch is a replacement solution that I suggest instead of http://patchwork.ozlabs.org/patch/174735/ since there is no need for a CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES config option in the NFC driver. It still has to be tested by someone having this board, but I'm very confident that it works since I have another PCB design based on the i.MX25 with a NAND Flash with the same timings that works fine using these clock settings. .../board/karo/tx25/lowlevel_init.S | 8 ++++++++ 1 file changed, 8 insertions(+)