| Message ID | 193496769.2411437.1344976374392.JavaMail.root@advansee.com |
|---|---|
| State | Accepted |
| Commit | e7619554173a9d9f72dc19f97a804afea135f07f |
| Delegated to: | Stefano Babic |
| Headers | show |
On 14/08/2012 22:32, Benoît Thébaudeau wrote: > The MFN bit-field of the PLL registers represents a signed value. See the > reference manual. > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > Cc: Stefano Babic <sbabic@denx.de> > --- Hi Benoît, > .../arch/arm/cpu/arm1136/mx35/generic.c | 9 ++++++--- > 1 file changed, 6 insertions(+), 3 deletions(-) > > diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c > index dba4903..e369c86 100644 > --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c > +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c > @@ -24,6 +24,7 @@ > */ > > #include <common.h> > +#include <div64.h> > #include <asm/io.h> > #include <asm/errno.h> > #include <asm/arch/imx-regs.h> > @@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0) > static u32 decode_pll(u32 reg, u32 infreq) > { > u32 mfi = (reg >> 10) & 0xf; > - u32 mfn = reg & 0x3f; > - u32 mfd = (reg >> 16) & 0x3f; > + s32 mfn = reg & 0x3ff; > + u32 mfd = (reg >> 16) & 0x3ff; The MFN is a signed value. But you are masking now 11 bits. According to the manual, bit 9-0 are MFN. You are taking in the mask the first bit of MFI, and this is wrong, isn't it ? Best regards, Stefano Babic
Am 01/09/2012 10:15, schrieb Stefano Babic: > On 14/08/2012 22:32, Benoît Thébaudeau wrote: >> The MFN bit-field of the PLL registers represents a signed value. See the >> reference manual. >> >> Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> >> Cc: Stefano Babic <sbabic@denx.de> >> --- > > Hi Benoît, > >> .../arch/arm/cpu/arm1136/mx35/generic.c | 9 ++++++--- >> 1 file changed, 6 insertions(+), 3 deletions(-) >> >> diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c >> index dba4903..e369c86 100644 >> --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c >> +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c >> @@ -24,6 +24,7 @@ >> */ >> >> #include <common.h> >> +#include <div64.h> >> #include <asm/io.h> >> #include <asm/errno.h> >> #include <asm/arch/imx-regs.h> >> @@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0) >> static u32 decode_pll(u32 reg, u32 infreq) >> { >> u32 mfi = (reg >> 10) & 0xf; >> - u32 mfn = reg & 0x3f; >> - u32 mfd = (reg >> 16) & 0x3f; >> + s32 mfn = reg & 0x3ff; >> + u32 mfd = (reg >> 16) & 0x3ff; > > The MFN is a signed value. But you are masking now 11 bits. According to > the manual, bit 9-0 are MFN. You are taking in the mask the first bit of > MFI, and this is wrong, isn't it ? Sorry, mask is correct Regards, Stefano
On 14/08/2012 22:32, Benoît Thébaudeau wrote: > The MFN bit-field of the PLL registers represents a signed value. See the > reference manual. > > Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> > Cc: Stefano Babic <sbabic@denx.de> > --- Applied to u-boot-imx, thanks. Best regards, Stefano Babic
diff --git u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c index dba4903..e369c86 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/arm1136/mx35/generic.c +++ u-boot-4d3c95f/arch/arm/cpu/arm1136/mx35/generic.c @@ -24,6 +24,7 @@ */ #include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -126,15 +127,17 @@ static int get_ahb_div(u32 pdr0) static u32 decode_pll(u32 reg, u32 infreq) { u32 mfi = (reg >> 10) & 0xf; - u32 mfn = reg & 0x3f; - u32 mfd = (reg >> 16) & 0x3f; + s32 mfn = reg & 0x3ff; + u32 mfd = (reg >> 16) & 0x3ff; u32 pd = (reg >> 26) & 0xf; mfi = mfi <= 5 ? 5 : mfi; + mfn = mfn >= 512 ? mfn - 1024 : mfn; mfd += 1; pd += 1; - return ((2 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; + return lldiv(2 * (u64)infreq * (mfi * mfd + mfn), + mfd * pd); } static u32 get_mcu_main_clk(void)
The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> --- .../arch/arm/cpu/arm1136/mx35/generic.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-)