| Message ID | 20240829013058.6178-6-minda.chen@starfivetech.com |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | Add Starfive JH7110 Cadence USB driver | expand |
On Wed, Aug 28, 2024 at 6:31 PM Minda Chen <minda.chen@starfivetech.com> wrote: > > For some JH7110 boards, USB host overcurent pin is not reserved, > To make USB host work, overcurrent pin must be disabled. So set the > pin default disabled in spl stage. > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > --- > arch/riscv/include/asm/arch-jh7110/gpio.h | 5 +++++ > board/starfive/visionfive2/spl.c | 3 +++ > 2 files changed, 8 insertions(+) > > diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h > index 90aa2f8a9e..be2a1e0d1c 100644 > --- a/arch/riscv/include/asm/arch-jh7110/gpio.h > +++ b/arch/riscv/include/asm/arch-jh7110/gpio.h > @@ -63,6 +63,11 @@ enum gpio_state { > GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ > ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) > > +#define SYS_IOMUX_DIN_DISABLED(gpi)\ > + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \ > + GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ > + ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) > + > #define SYS_IOMUX_SET_DS(gpio, ds) \ > clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ > GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT) > diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c > index b794b73b6b..388a06e4d9 100644 > --- a/board/starfive/visionfive2/spl.c > +++ b/board/starfive/visionfive2/spl.c > @@ -452,6 +452,9 @@ void board_init_f(ulong dummy) > JH7110_CLK_CPU_ROOT_MASK, > BIT(JH7110_CLK_CPU_ROOT_SHIFT)); > > + /* Set USB overcurrent overflow pin disable */ > + SYS_IOMUX_DIN_DISABLED(2); > + > ret = spl_board_init_f(); > if (ret) { > debug("spl_board_init_f init failed: %d\n", ret); > -- > 2.17.1 > As tested, this patch is required for the operating system after U-Boot to enable USB on at least Pine64 Star64 and Milk-V Mars CM Lite even if U-Boot does not adopt the other patches in this series. Can this be cherry-picked separate from the series? Tested-by: E Shattow <lucent@gmail.com>
diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h b/arch/riscv/include/asm/arch-jh7110/gpio.h index 90aa2f8a9e..be2a1e0d1c 100644 --- a/arch/riscv/include/asm/arch-jh7110/gpio.h +++ b/arch/riscv/include/asm/arch-jh7110/gpio.h @@ -63,6 +63,11 @@ enum gpio_state { GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) +#define SYS_IOMUX_DIN_DISABLED(gpi)\ + clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \ + GPIO_DIN_MASK << GPIO_SHIFT(gpi), \ + ((0x1) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi)) + #define SYS_IOMUX_SET_DS(gpio, ds) \ clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \ GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT) diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c index b794b73b6b..388a06e4d9 100644 --- a/board/starfive/visionfive2/spl.c +++ b/board/starfive/visionfive2/spl.c @@ -452,6 +452,9 @@ void board_init_f(ulong dummy) JH7110_CLK_CPU_ROOT_MASK, BIT(JH7110_CLK_CPU_ROOT_SHIFT)); + /* Set USB overcurrent overflow pin disable */ + SYS_IOMUX_DIN_DISABLED(2); + ret = spl_board_init_f(); if (ret) { debug("spl_board_init_f init failed: %d\n", ret);
For some JH7110 boards, USB host overcurent pin is not reserved, To make USB host work, overcurrent pin must be disabled. So set the pin default disabled in spl stage. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> --- arch/riscv/include/asm/arch-jh7110/gpio.h | 5 +++++ board/starfive/visionfive2/spl.c | 3 +++ 2 files changed, 8 insertions(+)