diff mbox series

[14/15] cxl/aer/pci: Export pci_aer_unmask_internal_errors()

Message ID 20241008221657.1130181-15-terry.bowman@amd.com
State New
Headers show
Series Enable CXL PCIe port protocol error handling and logging | expand

Commit Message

Bowman, Terry Oct. 8, 2024, 10:16 p.m. UTC 
The CXL driver needs to enable AER correctable and uncorrectable internal
errors in order to receive notification of protocol
errors. pci_aer_unmask_internal_errors() is currently defined as
'static' in the AER service driver.

Update the AER service driver, exporting pci_aer_unmask_internal_errors()
to CXL namespace.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
---
 drivers/pci/pcie/aer.c | 6 ++++--
 include/linux/aer.h    | 2 ++
 2 files changed, 6 insertions(+), 2 deletions(-)

Comments

Jonathan Cameron Oct. 16, 2024, 5:22 p.m. UTC | #1 
On Tue, 8 Oct 2024 17:16:56 -0500
Terry Bowman <terry.bowman@amd.com> wrote:

> The CXL driver needs to enable AER correctable and uncorrectable internal
> errors in order to receive notification of protocol
> errors. pci_aer_unmask_internal_errors() is currently defined as
> 'static' in the AER service driver.
> 
> Update the AER service driver, exporting pci_aer_unmask_internal_errors()
> to CXL namespace.
> 
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

(subject to suggestion we just enable internal errors for all devices
and sit back and watch for error reports :))
diff mbox series

Patch

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 81a19028c4e7..1b4004932084 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -962,7 +962,6 @@  static bool is_internal_error(struct aer_err_info *info)
 	return info->status & PCI_ERR_UNC_INTN;
 }
 
-#ifdef CONFIG_PCIEAER_CXL
 /**
  * pci_aer_unmask_internal_errors - unmask internal errors
  * @dev: pointer to the pcie_dev data structure
@@ -973,7 +972,7 @@  static bool is_internal_error(struct aer_err_info *info)
  * Note: AER must be enabled and supported by the device which must be
  * checked in advance, e.g. with pcie_aer_is_native().
  */
-static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
+void pci_aer_unmask_internal_errors(struct pci_dev *dev)
 {
 	int aer = dev->aer_cap;
 	u32 mask;
@@ -986,6 +985,9 @@  static void pci_aer_unmask_internal_errors(struct pci_dev *dev)
 	mask &= ~PCI_ERR_COR_INTERNAL;
 	pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);
 }
+EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, CXL);
+
+#ifdef CONFIG_PCIEAER_CXL
 
 static bool is_cxl_mem_dev(struct pci_dev *dev)
 {
diff --git a/include/linux/aer.h b/include/linux/aer.h
index 67fd04c5ae2b..c43d2b60b992 100644
--- a/include/linux/aer.h
+++ b/include/linux/aer.h
@@ -69,5 +69,7 @@  struct cxl_port_err_hndlrs {
 void register_cxl_port_hndlrs(struct cxl_port_err_hndlrs *_cxl_port_hndlrs);
 void unregister_cxl_port_hndlrs(void);
 struct cxl_port_err_hndlrs *find_cxl_port_hndlrs(void);
+
+void pci_aer_unmask_internal_errors(struct pci_dev *dev);
 #endif //_AER_H_