diff mbox series

[3/3] AArch64: use movi d0, #0 to clear SVE registers instead of mov z0.d, #0

Message ID Zwz4dVlhRhAS7LJy@arm.com
State New
Headers show
Series [1/3] AArch64: update testsuite to account for new zero moves | expand

Commit Message

Tamar Christina Oct. 14, 2024, 10:54 a.m. UTC 
Hi All,

This patch changes SVE to use Adv. SIMD fmov 0 to clear SVE registers when not
in SVE streaming mode.  As the Neoverse Software Optimization guides indicate
SVE mov #0 is not a zero cost move.

When In streaming mode we continue to use SVE's mov to clear the registers.

Tests have already been updated.

Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.

Ok for master?

Thanks,
Tamar

gcc/ChangeLog:

	* config/aarch64/aarch64.cc (aarch64_output_sve_mov_immediate): Use
	fmov for SVE zeros.

---




--

Comments

Richard Sandiford Oct. 14, 2024, 6:29 p.m. UTC | #1 
Tamar Christina <tamar.christina@arm.com> writes:
> Hi All,
>
> This patch changes SVE to use Adv. SIMD fmov 0 to clear SVE registers when not

s/fmov/movi/, here and below.

OK with that change, thanks.

Richard

> in SVE streaming mode.  As the Neoverse Software Optimization guides indicate
> SVE mov #0 is not a zero cost move.
>
> When In streaming mode we continue to use SVE's mov to clear the registers.
>
> Tests have already been updated.
>
> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
>
> Ok for master?
>
> Thanks,
> Tamar
>
> gcc/ChangeLog:
>
> 	* config/aarch64/aarch64.cc (aarch64_output_sve_mov_immediate): Use
> 	fmov for SVE zeros.
>
> ---
>
> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
> index 9142a1eb319c9d596eaa8ab723c5abea60818438..a9d8f9fbeddd0f4269c1671f8d1b504c68ef3910 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -25515,8 +25515,11 @@ aarch64_output_sve_mov_immediate (rtx const_vector)
>  	}
>      }
>  
> -  snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC,
> -	    element_char, INTVAL (info.u.mov.value));
> +  if (info.u.mov.value == const0_rtx && TARGET_NON_STREAMING)
> +    snprintf (templ, sizeof (templ), "movi\t%%d0, #0");
> +  else
> +    snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC,
> +	      element_char, INTVAL (info.u.mov.value));
>    return templ;
>  }
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc
index 9142a1eb319c9d596eaa8ab723c5abea60818438..a9d8f9fbeddd0f4269c1671f8d1b504c68ef3910 100644
--- a/gcc/config/aarch64/aarch64.cc
+++ b/gcc/config/aarch64/aarch64.cc
@@ -25515,8 +25515,11 @@  aarch64_output_sve_mov_immediate (rtx const_vector)
 	}
     }
 
-  snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC,
-	    element_char, INTVAL (info.u.mov.value));
+  if (info.u.mov.value == const0_rtx && TARGET_NON_STREAMING)
+    snprintf (templ, sizeof (templ), "movi\t%%d0, #0");
+  else
+    snprintf (templ, sizeof (templ), "mov\t%%0.%c, #" HOST_WIDE_INT_PRINT_DEC,
+	      element_char, INTVAL (info.u.mov.value));
   return templ;
 }