| Message ID | 20240904132650.2720446-28-christophe.lyon@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | arm: [MVE intrinsics] Re-implement more intrinsics | expand |
On 04/09/2024 14:26, Christophe Lyon wrote: > Like with vddup/vidup, we use code_for_mve_q_wb_u_insn, so we can drop > the expanders and their declarations as builtins, now useless. > > 2024-08-28 Christophe Lyon <christophe.lyon@linaro.org> > > gcc/ > * config/arm/arm-builtins.cc > (arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers): Delete. > * config/arm/arm_mve_builtins.def (viwdupq_wb_u, vdwdupq_wb_u) > (viwdupq_m_wb_u, vdwdupq_m_wb_u, viwdupq_m_n_u, vdwdupq_m_n_u) > (vdwdupq_n_u, viwdupq_n_u): Delete. > * config/arm/mve.md (mve_vdwdupq_n_u<mode>): Delete. > (mve_vdwdupq_wb_u<mode>): Delete. > (mve_vdwdupq_m_n_u<mode>): Delete. > (mve_vdwdupq_m_wb_u<mode>): Delete. OK. R. > --- > gcc/config/arm/arm-builtins.cc | 7 --- > gcc/config/arm/arm_mve_builtins.def | 8 --- > gcc/config/arm/mve.md | 75 ----------------------------- > 3 files changed, 90 deletions(-) > > diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc > index c9d50bf8fbb..697b91911dd 100644 > --- a/gcc/config/arm/arm-builtins.cc > +++ b/gcc/config/arm/arm-builtins.cc > @@ -755,13 +755,6 @@ arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_pointer, qualifier_predicate}; > #define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) > > -static enum arm_type_qualifiers > -arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] > - = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, > - qualifier_unsigned, qualifier_immediate, qualifier_predicate }; > -#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS \ > - (arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers) > - > static enum arm_type_qualifiers > arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] > = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; > diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def > index 7e88db4e4c3..f6962cd8cf5 100644 > --- a/gcc/config/arm/arm_mve_builtins.def > +++ b/gcc/config/arm/arm_mve_builtins.def > @@ -799,14 +799,6 @@ VAR1 (STRSU_P, vstrdq_scatter_offset_p_u, v2di) > VAR1 (STRSU_P, vstrdq_scatter_shifted_offset_p_u, v2di) > VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si) > VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_wb_u, v16qi, v4si, v8hi) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_wb_u, v16qi, v4si, v8hi) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_wb_u, v16qi, v8hi, v4si) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_wb_u, v16qi, v8hi, v4si) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_n_u, v16qi, v8hi, v4si) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) > -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) > VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si) > VAR1 (STRSBWBU, vstrdq_scatter_base_wb_u, v2di) > VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_u, v4si) > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 72a7e4dc868..0507e117f51 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -5120,41 +5120,6 @@ (define_insn "@mve_<mve_insn>q_m_wb_u<mode>_insn" > [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_u<mode>_insn")) > (set_attr "length""8")]) > > -;; > -;; [vdwdupq_n_u]) > -;; > -(define_expand "mve_vdwdupq_n_u<mode>" > - [(match_operand:MVE_2 0 "s_register_operand") > - (match_operand:SI 1 "s_register_operand") > - (match_operand:DI 2 "s_register_operand") > - (match_operand:SI 3 "mve_imm_selective_upto_8")] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_wb = gen_reg_rtx (SImode); > - emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb, > - operands[1], operands[2], > - operands[3])); > - DONE; > -}) > - > -;; > -;; [vdwdupq_wb_u]) > -;; > -(define_expand "mve_vdwdupq_wb_u<mode>" > - [(match_operand:SI 0 "s_register_operand") > - (match_operand:SI 1 "s_register_operand") > - (match_operand:DI 2 "s_register_operand") > - (match_operand:SI 3 "mve_imm_selective_upto_8") > - (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_vec = gen_reg_rtx (<MODE>mode); > - emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0], > - operands[1], operands[2], > - operands[3])); > - DONE; > -}) > - > ;; > ;; [vdwdupq_wb_u_insn, viwdupq_wb_u_insn] > ;; > @@ -5174,46 +5139,6 @@ (define_insn "@mve_<mve_insn>q_wb_u<mode>_insn" > [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_wb_u<mode>_insn")) > (set_attr "type" "mve_move")]) > > -;; > -;; [vdwdupq_m_n_u]) > -;; > -(define_expand "mve_vdwdupq_m_n_u<mode>" > - [(match_operand:MVE_2 0 "s_register_operand") > - (match_operand:MVE_2 1 "s_register_operand") > - (match_operand:SI 2 "s_register_operand") > - (match_operand:DI 3 "s_register_operand") > - (match_operand:SI 4 "mve_imm_selective_upto_8") > - (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_wb = gen_reg_rtx (SImode); > - emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, > - operands[1], operands[2], > - operands[3], operands[4], > - operands[5])); > - DONE; > -}) > - > -;; > -;; [vdwdupq_m_wb_u]) > -;; > -(define_expand "mve_vdwdupq_m_wb_u<mode>" > - [(match_operand:SI 0 "s_register_operand") > - (match_operand:MVE_2 1 "s_register_operand") > - (match_operand:SI 2 "s_register_operand") > - (match_operand:DI 3 "s_register_operand") > - (match_operand:SI 4 "mve_imm_selective_upto_8") > - (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] > - "TARGET_HAVE_MVE" > -{ > - rtx ignore_vec = gen_reg_rtx (<MODE>mode); > - emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], > - operands[1], operands[2], > - operands[3], operands[4], > - operands[5])); > - DONE; > -}) > - > ;; > ;; [vdwdupq_m_wb_u_insn, viwdupq_m_wb_u_insn] > ;;
diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.cc index c9d50bf8fbb..697b91911dd 100644 --- a/gcc/config/arm/arm-builtins.cc +++ b/gcc/config/arm/arm-builtins.cc @@ -755,13 +755,6 @@ arm_ldru_z_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_pointer, qualifier_predicate}; #define LDRU_Z_QUALIFIERS (arm_ldru_z_qualifiers) -static enum arm_type_qualifiers -arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] - = { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, - qualifier_unsigned, qualifier_immediate, qualifier_predicate }; -#define QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS \ - (arm_quinop_unone_unone_unone_unone_imm_pred_qualifiers) - static enum arm_type_qualifiers arm_ldrgbwbxu_qualifiers[SIMD_MAX_BUILTIN_ARGS] = { qualifier_unsigned, qualifier_unsigned, qualifier_immediate}; diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 7e88db4e4c3..f6962cd8cf5 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -799,14 +799,6 @@ VAR1 (STRSU_P, vstrdq_scatter_offset_p_u, v2di) VAR1 (STRSU_P, vstrdq_scatter_shifted_offset_p_u, v2di) VAR1 (STRSU_P, vstrwq_scatter_offset_p_u, v4si) VAR1 (STRSU_P, vstrwq_scatter_shifted_offset_p_u, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_wb_u, v16qi, v4si, v8hi) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_wb_u, v16qi, v4si, v8hi) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_wb_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_wb_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, viwdupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED, vdwdupq_m_n_u, v16qi, v8hi, v4si) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vdwdupq_n_u, v16qi, v4si, v8hi) -VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, viwdupq_n_u, v16qi, v4si, v8hi) VAR1 (STRSBWBU, vstrwq_scatter_base_wb_u, v4si) VAR1 (STRSBWBU, vstrdq_scatter_base_wb_u, v2di) VAR1 (STRSBWBU_P, vstrwq_scatter_base_wb_p_u, v4si) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 72a7e4dc868..0507e117f51 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -5120,41 +5120,6 @@ (define_insn "@mve_<mve_insn>q_m_wb_u<mode>_insn" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_u<mode>_insn")) (set_attr "length""8")]) -;; -;; [vdwdupq_n_u]) -;; -(define_expand "mve_vdwdupq_n_u<mode>" - [(match_operand:MVE_2 0 "s_register_operand") - (match_operand:SI 1 "s_register_operand") - (match_operand:DI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_selective_upto_8")] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (SImode); - emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (operands[0], ignore_wb, - operands[1], operands[2], - operands[3])); - DONE; -}) - -;; -;; [vdwdupq_wb_u]) -;; -(define_expand "mve_vdwdupq_wb_u<mode>" - [(match_operand:SI 0 "s_register_operand") - (match_operand:SI 1 "s_register_operand") - (match_operand:DI 2 "s_register_operand") - (match_operand:SI 3 "mve_imm_selective_upto_8") - (unspec:MVE_2 [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (<MODE>mode); - emit_insn (gen_mve_vdwdupq_wb_u<mode>_insn (ignore_vec, operands[0], - operands[1], operands[2], - operands[3])); - DONE; -}) - ;; ;; [vdwdupq_wb_u_insn, viwdupq_wb_u_insn] ;; @@ -5174,46 +5139,6 @@ (define_insn "@mve_<mve_insn>q_wb_u<mode>_insn" [(set (attr "mve_unpredicated_insn") (symbol_ref "CODE_FOR_mve_<mve_insn>q_wb_u<mode>_insn")) (set_attr "type" "mve_move")]) -;; -;; [vdwdupq_m_n_u]) -;; -(define_expand "mve_vdwdupq_m_n_u<mode>" - [(match_operand:MVE_2 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:DI 3 "s_register_operand") - (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] - "TARGET_HAVE_MVE" -{ - rtx ignore_wb = gen_reg_rtx (SImode); - emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (operands[0], ignore_wb, - operands[1], operands[2], - operands[3], operands[4], - operands[5])); - DONE; -}) - -;; -;; [vdwdupq_m_wb_u]) -;; -(define_expand "mve_vdwdupq_m_wb_u<mode>" - [(match_operand:SI 0 "s_register_operand") - (match_operand:MVE_2 1 "s_register_operand") - (match_operand:SI 2 "s_register_operand") - (match_operand:DI 3 "s_register_operand") - (match_operand:SI 4 "mve_imm_selective_upto_8") - (match_operand:<MVE_VPRED> 5 "vpr_register_operand")] - "TARGET_HAVE_MVE" -{ - rtx ignore_vec = gen_reg_rtx (<MODE>mode); - emit_insn (gen_mve_vdwdupq_m_wb_u<mode>_insn (ignore_vec, operands[0], - operands[1], operands[2], - operands[3], operands[4], - operands[5])); - DONE; -}) - ;; ;; [vdwdupq_m_wb_u_insn, viwdupq_m_wb_u_insn] ;;