| Message ID | 20241004064733.1362850-2-karol.kolacinski@intel.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [iwl-next] ice: Add in/out PTP pin delays | expand |
On Fri, Oct 04, 2024 at 08:47:13AM +0200, Karol Kolacinski wrote: > HW can have different input/output delays for each of the pins. > Add a field in ice_ptp_pin_desc structure to reflect that. > > Implement external timestamp delay compensation. > > Remove existing definitions and wrappers for periodic output propagation > delays. > > Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> ... > @@ -1767,6 +1778,7 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan, > static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq, > int on) > { > + unsigned int gpio_pin, prop_delay; > u64 clk, period, start, phase; > struct ice_hw *hw = &pf->hw; > unsigned int gpio_pin; The local variable gpio_pin is now declared twice :(
Hi Karol, kernel test robot noticed the following build errors: [auto build test ERROR on f2589ad16e14b7102f1411e3385a2abf07076406] url: https://github.com/intel-lab-lkp/linux/commits/Karol-Kolacinski/ice-Add-in-out-PTP-pin-delays/20241004-144802 base: f2589ad16e14b7102f1411e3385a2abf07076406 patch link: https://lore.kernel.org/r/20241004064733.1362850-2-karol.kolacinski%40intel.com patch subject: [PATCH iwl-next] ice: Add in/out PTP pin delays config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20241005/202410051435.O9bgxFKe-lkp@intel.com/config) compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241005/202410051435.O9bgxFKe-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410051435.O9bgxFKe-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/net/ethernet/intel/ice/ice_ptp.c:1784:15: error: redefinition of 'gpio_pin' 1784 | unsigned int gpio_pin; | ^ drivers/net/ethernet/intel/ice/ice_ptp.c:1781:15: note: previous definition is here 1781 | unsigned int gpio_pin, prop_delay; | ^ 1 error generated. -- >> drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5033:29: error: use of undeclared identifier 'ICE_E810_E830_SYNC_DELAY' 5033 | ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); | ^ drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5341:29: error: use of undeclared identifier 'ICE_E810_E830_SYNC_DELAY' 5341 | ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); | ^ 2 errors generated. Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for MODVERSIONS Depends on [n]: MODULES [=y] && !COMPILE_TEST [=y] Selected by [y]: - RANDSTRUCT_FULL [=y] && (CC_HAS_RANDSTRUCT [=y] || GCC_PLUGINS [=n]) && MODULES [=y] vim +/gpio_pin +1784 drivers/net/ethernet/intel/ice/ice_ptp.c 172db5f91d5f7b Maciej Machnikowski 2021-06-16 1766 5a078a58ade86d Karol Kolacinski 2024-08-30 1767 /** 5a078a58ade86d Karol Kolacinski 2024-08-30 1768 * ice_ptp_cfg_perout - Configure clock to generate periodic wave 5a078a58ade86d Karol Kolacinski 2024-08-30 1769 * @pf: Board private structure 5a078a58ade86d Karol Kolacinski 2024-08-30 1770 * @rq: Periodic output request 5a078a58ade86d Karol Kolacinski 2024-08-30 1771 * @on: Enable/disable flag 5a078a58ade86d Karol Kolacinski 2024-08-30 1772 * 5a078a58ade86d Karol Kolacinski 2024-08-30 1773 * Configure the internal clock generator modules to generate the clock wave of 5a078a58ade86d Karol Kolacinski 2024-08-30 1774 * specified period. 5a078a58ade86d Karol Kolacinski 2024-08-30 1775 * 5a078a58ade86d Karol Kolacinski 2024-08-30 1776 * Return: 0 on success, negative error code otherwise 5a078a58ade86d Karol Kolacinski 2024-08-30 1777 */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1778 static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq, 5a078a58ade86d Karol Kolacinski 2024-08-30 1779 int on) 5a078a58ade86d Karol Kolacinski 2024-08-30 1780 { 718647161517f7 Karol Kolacinski 2024-10-04 1781 unsigned int gpio_pin, prop_delay; 5a078a58ade86d Karol Kolacinski 2024-08-30 1782 u64 clk, period, start, phase; 5a078a58ade86d Karol Kolacinski 2024-08-30 1783 struct ice_hw *hw = &pf->hw; 5a078a58ade86d Karol Kolacinski 2024-08-30 @1784 unsigned int gpio_pin; 5a078a58ade86d Karol Kolacinski 2024-08-30 1785 int pin_desc_idx; 5a078a58ade86d Karol Kolacinski 2024-08-30 1786 5a078a58ade86d Karol Kolacinski 2024-08-30 1787 if (rq->flags & ~PTP_PEROUT_PHASE) 5a078a58ade86d Karol Kolacinski 2024-08-30 1788 return -EOPNOTSUPP; 5a078a58ade86d Karol Kolacinski 2024-08-30 1789 5a078a58ade86d Karol Kolacinski 2024-08-30 1790 pin_desc_idx = ice_ptp_find_pin_idx(pf, PTP_PF_PEROUT, rq->index); 5a078a58ade86d Karol Kolacinski 2024-08-30 1791 if (pin_desc_idx < 0) 5a078a58ade86d Karol Kolacinski 2024-08-30 1792 return -EIO; 5a078a58ade86d Karol Kolacinski 2024-08-30 1793 5a078a58ade86d Karol Kolacinski 2024-08-30 1794 gpio_pin = pf->ptp.ice_pin_desc[pin_desc_idx].gpio[1]; 718647161517f7 Karol Kolacinski 2024-10-04 1795 prop_delay = pf->ptp.ice_pin_desc[pin_desc_idx].delay[1]; 5a078a58ade86d Karol Kolacinski 2024-08-30 1796 period = rq->period.sec * NSEC_PER_SEC + rq->period.nsec; 5a078a58ade86d Karol Kolacinski 2024-08-30 1797 5a078a58ade86d Karol Kolacinski 2024-08-30 1798 /* If we're disabling the output or period is 0, clear out CLKO and TGT 5a078a58ade86d Karol Kolacinski 2024-08-30 1799 * and keep output level low. 5a078a58ade86d Karol Kolacinski 2024-08-30 1800 */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1801 if (!on || !period) 5a078a58ade86d Karol Kolacinski 2024-08-30 1802 return ice_ptp_write_perout(hw, rq->index, gpio_pin, 0, 0); 5a078a58ade86d Karol Kolacinski 2024-08-30 1803 5a078a58ade86d Karol Kolacinski 2024-08-30 1804 if (strncmp(pf->ptp.pin_desc[pin_desc_idx].name, "1PPS", 64) == 0 && 001459cacff09e Karol Kolacinski 2024-09-30 1805 period != NSEC_PER_SEC && hw->mac_type == ICE_MAC_GENERIC) { 5a078a58ade86d Karol Kolacinski 2024-08-30 1806 dev_err(ice_pf_to_dev(pf), "1PPS pin supports only 1 s period\n"); 5a078a58ade86d Karol Kolacinski 2024-08-30 1807 return -EOPNOTSUPP; 5a078a58ade86d Karol Kolacinski 2024-08-30 1808 } 5a078a58ade86d Karol Kolacinski 2024-08-30 1809 5a078a58ade86d Karol Kolacinski 2024-08-30 1810 if (period & 0x1) { 5a078a58ade86d Karol Kolacinski 2024-08-30 1811 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n"); 5a078a58ade86d Karol Kolacinski 2024-08-30 1812 return -EIO; 5a078a58ade86d Karol Kolacinski 2024-08-30 1813 } 5a078a58ade86d Karol Kolacinski 2024-08-30 1814 5a078a58ade86d Karol Kolacinski 2024-08-30 1815 start = rq->start.sec * NSEC_PER_SEC + rq->start.nsec; 5a078a58ade86d Karol Kolacinski 2024-08-30 1816 5a078a58ade86d Karol Kolacinski 2024-08-30 1817 /* If PTP_PEROUT_PHASE is set, rq has phase instead of start time */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1818 if (rq->flags & PTP_PEROUT_PHASE) 5a078a58ade86d Karol Kolacinski 2024-08-30 1819 phase = start; 5a078a58ade86d Karol Kolacinski 2024-08-30 1820 else 5a078a58ade86d Karol Kolacinski 2024-08-30 1821 div64_u64_rem(start, period, &phase); 5a078a58ade86d Karol Kolacinski 2024-08-30 1822 5a078a58ade86d Karol Kolacinski 2024-08-30 1823 /* If we have only phase or start time is in the past, start the timer 5a078a58ade86d Karol Kolacinski 2024-08-30 1824 * at the next multiple of period, maintaining phase. 5a078a58ade86d Karol Kolacinski 2024-08-30 1825 */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1826 clk = ice_ptp_read_src_clk_reg(pf, NULL); 718647161517f7 Karol Kolacinski 2024-10-04 1827 if (rq->flags & PTP_PEROUT_PHASE || start <= clk - prop_delay) 5a078a58ade86d Karol Kolacinski 2024-08-30 1828 start = div64_u64(clk + period - 1, period) * period + phase; 5a078a58ade86d Karol Kolacinski 2024-08-30 1829 5a078a58ade86d Karol Kolacinski 2024-08-30 1830 /* Compensate for propagation delay from the generator to the pin. */ 718647161517f7 Karol Kolacinski 2024-10-04 1831 start -= prop_delay; 5a078a58ade86d Karol Kolacinski 2024-08-30 1832 5a078a58ade86d Karol Kolacinski 2024-08-30 1833 return ice_ptp_write_perout(hw, rq->index, gpio_pin, start, period); 172db5f91d5f7b Maciej Machnikowski 2021-06-16 1834 } 172db5f91d5f7b Maciej Machnikowski 2021-06-16 1835
Hi Karol, kernel test robot noticed the following build errors: [auto build test ERROR on f2589ad16e14b7102f1411e3385a2abf07076406] url: https://github.com/intel-lab-lkp/linux/commits/Karol-Kolacinski/ice-Add-in-out-PTP-pin-delays/20241004-144802 base: f2589ad16e14b7102f1411e3385a2abf07076406 patch link: https://lore.kernel.org/r/20241004064733.1362850-2-karol.kolacinski%40intel.com patch subject: [PATCH iwl-next] ice: Add in/out PTP pin delays config: alpha-allyesconfig (https://download.01.org/0day-ci/archive/20241005/202410051418.lLY7SXXp-lkp@intel.com/config) compiler: alpha-linux-gcc (GCC) 13.3.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241005/202410051418.lLY7SXXp-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410051418.lLY7SXXp-lkp@intel.com/ All errors (new ones prefixed by >>): drivers/net/ethernet/intel/ice/ice_ptp.c: In function 'ice_ptp_cfg_perout': >> drivers/net/ethernet/intel/ice/ice_ptp.c:1784:22: error: redeclaration of 'gpio_pin' with no linkage 1784 | unsigned int gpio_pin; | ^~~~~~~~ drivers/net/ethernet/intel/ice/ice_ptp.c:1781:22: note: previous declaration of 'gpio_pin' with type 'unsigned int' 1781 | unsigned int gpio_pin, prop_delay; | ^~~~~~~~ -- drivers/net/ethernet/intel/ice/ice_ptp_hw.c: In function 'ice_ptp_init_phc_e810': >> drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5033:36: error: 'ICE_E810_E830_SYNC_DELAY' undeclared (first use in this function) 5033 | ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); | ^~~~~~~~~~~~~~~~~~~~~~~~ drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5033:36: note: each undeclared identifier is reported only once for each function it appears in drivers/net/ethernet/intel/ice/ice_ptp_hw.c: In function 'ice_ptp_init_phc_e830': drivers/net/ethernet/intel/ice/ice_ptp_hw.c:5341:36: error: 'ICE_E810_E830_SYNC_DELAY' undeclared (first use in this function) 5341 | ice_ptp_cfg_sync_delay(hw, ICE_E810_E830_SYNC_DELAY); | ^~~~~~~~~~~~~~~~~~~~~~~~ vim +/gpio_pin +1784 drivers/net/ethernet/intel/ice/ice_ptp.c 172db5f91d5f7b Maciej Machnikowski 2021-06-16 1766 5a078a58ade86d Karol Kolacinski 2024-08-30 1767 /** 5a078a58ade86d Karol Kolacinski 2024-08-30 1768 * ice_ptp_cfg_perout - Configure clock to generate periodic wave 5a078a58ade86d Karol Kolacinski 2024-08-30 1769 * @pf: Board private structure 5a078a58ade86d Karol Kolacinski 2024-08-30 1770 * @rq: Periodic output request 5a078a58ade86d Karol Kolacinski 2024-08-30 1771 * @on: Enable/disable flag 5a078a58ade86d Karol Kolacinski 2024-08-30 1772 * 5a078a58ade86d Karol Kolacinski 2024-08-30 1773 * Configure the internal clock generator modules to generate the clock wave of 5a078a58ade86d Karol Kolacinski 2024-08-30 1774 * specified period. 5a078a58ade86d Karol Kolacinski 2024-08-30 1775 * 5a078a58ade86d Karol Kolacinski 2024-08-30 1776 * Return: 0 on success, negative error code otherwise 5a078a58ade86d Karol Kolacinski 2024-08-30 1777 */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1778 static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq, 5a078a58ade86d Karol Kolacinski 2024-08-30 1779 int on) 5a078a58ade86d Karol Kolacinski 2024-08-30 1780 { 718647161517f7 Karol Kolacinski 2024-10-04 1781 unsigned int gpio_pin, prop_delay; 5a078a58ade86d Karol Kolacinski 2024-08-30 1782 u64 clk, period, start, phase; 5a078a58ade86d Karol Kolacinski 2024-08-30 1783 struct ice_hw *hw = &pf->hw; 5a078a58ade86d Karol Kolacinski 2024-08-30 @1784 unsigned int gpio_pin; 5a078a58ade86d Karol Kolacinski 2024-08-30 1785 int pin_desc_idx; 5a078a58ade86d Karol Kolacinski 2024-08-30 1786 5a078a58ade86d Karol Kolacinski 2024-08-30 1787 if (rq->flags & ~PTP_PEROUT_PHASE) 5a078a58ade86d Karol Kolacinski 2024-08-30 1788 return -EOPNOTSUPP; 5a078a58ade86d Karol Kolacinski 2024-08-30 1789 5a078a58ade86d Karol Kolacinski 2024-08-30 1790 pin_desc_idx = ice_ptp_find_pin_idx(pf, PTP_PF_PEROUT, rq->index); 5a078a58ade86d Karol Kolacinski 2024-08-30 1791 if (pin_desc_idx < 0) 5a078a58ade86d Karol Kolacinski 2024-08-30 1792 return -EIO; 5a078a58ade86d Karol Kolacinski 2024-08-30 1793 5a078a58ade86d Karol Kolacinski 2024-08-30 1794 gpio_pin = pf->ptp.ice_pin_desc[pin_desc_idx].gpio[1]; 718647161517f7 Karol Kolacinski 2024-10-04 1795 prop_delay = pf->ptp.ice_pin_desc[pin_desc_idx].delay[1]; 5a078a58ade86d Karol Kolacinski 2024-08-30 1796 period = rq->period.sec * NSEC_PER_SEC + rq->period.nsec; 5a078a58ade86d Karol Kolacinski 2024-08-30 1797 5a078a58ade86d Karol Kolacinski 2024-08-30 1798 /* If we're disabling the output or period is 0, clear out CLKO and TGT 5a078a58ade86d Karol Kolacinski 2024-08-30 1799 * and keep output level low. 5a078a58ade86d Karol Kolacinski 2024-08-30 1800 */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1801 if (!on || !period) 5a078a58ade86d Karol Kolacinski 2024-08-30 1802 return ice_ptp_write_perout(hw, rq->index, gpio_pin, 0, 0); 5a078a58ade86d Karol Kolacinski 2024-08-30 1803 5a078a58ade86d Karol Kolacinski 2024-08-30 1804 if (strncmp(pf->ptp.pin_desc[pin_desc_idx].name, "1PPS", 64) == 0 && 001459cacff09e Karol Kolacinski 2024-09-30 1805 period != NSEC_PER_SEC && hw->mac_type == ICE_MAC_GENERIC) { 5a078a58ade86d Karol Kolacinski 2024-08-30 1806 dev_err(ice_pf_to_dev(pf), "1PPS pin supports only 1 s period\n"); 5a078a58ade86d Karol Kolacinski 2024-08-30 1807 return -EOPNOTSUPP; 5a078a58ade86d Karol Kolacinski 2024-08-30 1808 } 5a078a58ade86d Karol Kolacinski 2024-08-30 1809 5a078a58ade86d Karol Kolacinski 2024-08-30 1810 if (period & 0x1) { 5a078a58ade86d Karol Kolacinski 2024-08-30 1811 dev_err(ice_pf_to_dev(pf), "CLK Period must be an even value\n"); 5a078a58ade86d Karol Kolacinski 2024-08-30 1812 return -EIO; 5a078a58ade86d Karol Kolacinski 2024-08-30 1813 } 5a078a58ade86d Karol Kolacinski 2024-08-30 1814 5a078a58ade86d Karol Kolacinski 2024-08-30 1815 start = rq->start.sec * NSEC_PER_SEC + rq->start.nsec; 5a078a58ade86d Karol Kolacinski 2024-08-30 1816 5a078a58ade86d Karol Kolacinski 2024-08-30 1817 /* If PTP_PEROUT_PHASE is set, rq has phase instead of start time */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1818 if (rq->flags & PTP_PEROUT_PHASE) 5a078a58ade86d Karol Kolacinski 2024-08-30 1819 phase = start; 5a078a58ade86d Karol Kolacinski 2024-08-30 1820 else 5a078a58ade86d Karol Kolacinski 2024-08-30 1821 div64_u64_rem(start, period, &phase); 5a078a58ade86d Karol Kolacinski 2024-08-30 1822 5a078a58ade86d Karol Kolacinski 2024-08-30 1823 /* If we have only phase or start time is in the past, start the timer 5a078a58ade86d Karol Kolacinski 2024-08-30 1824 * at the next multiple of period, maintaining phase. 5a078a58ade86d Karol Kolacinski 2024-08-30 1825 */ 5a078a58ade86d Karol Kolacinski 2024-08-30 1826 clk = ice_ptp_read_src_clk_reg(pf, NULL); 718647161517f7 Karol Kolacinski 2024-10-04 1827 if (rq->flags & PTP_PEROUT_PHASE || start <= clk - prop_delay) 5a078a58ade86d Karol Kolacinski 2024-08-30 1828 start = div64_u64(clk + period - 1, period) * period + phase; 5a078a58ade86d Karol Kolacinski 2024-08-30 1829 5a078a58ade86d Karol Kolacinski 2024-08-30 1830 /* Compensate for propagation delay from the generator to the pin. */ 718647161517f7 Karol Kolacinski 2024-10-04 1831 start -= prop_delay; 5a078a58ade86d Karol Kolacinski 2024-08-30 1832 5a078a58ade86d Karol Kolacinski 2024-08-30 1833 return ice_ptp_write_perout(hw, rq->index, gpio_pin, start, period); 172db5f91d5f7b Maciej Machnikowski 2021-06-16 1834 } 172db5f91d5f7b Maciej Machnikowski 2021-06-16 1835
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 9bc22620f838..f5f51af33716 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -16,28 +16,28 @@ static const char ice_pin_names[][64] = { }; static const struct ice_ptp_pin_desc ice_pin_desc_e82x[] = { - /* name, gpio */ - { TIME_SYNC, { 4, -1 }}, - { ONE_PPS, { -1, 5 }}, + /* name, gpio, delay */ + { TIME_SYNC, { 4, -1 }, { 0, 0 }}, + { ONE_PPS, { -1, 5 }, { 0, 11 }}, }; static const struct ice_ptp_pin_desc ice_pin_desc_e825c[] = { - /* name, gpio */ - { SDP0, { 0, 0 }}, - { SDP1, { 1, 1 }}, - { SDP2, { 2, 2 }}, - { SDP3, { 3, 3 }}, - { TIME_SYNC, { 4, -1 }}, - { ONE_PPS, { -1, 5 }}, + /* name, gpio, delay */ + { SDP0, { 0, 0 }, { 15, 14 }}, + { SDP1, { 1, 1 }, { 15, 14 }}, + { SDP2, { 2, 2 }, { 15, 14 }}, + { SDP3, { 3, 3 }, { 15, 14 }}, + { TIME_SYNC, { 4, -1 }, { 11, 0 }}, + { ONE_PPS, { -1, 5 }, { 0, 9 }}, }; static const struct ice_ptp_pin_desc ice_pin_desc_e810[] = { - /* name, gpio */ - { SDP0, { 0, 0 }}, - { SDP1, { 1, 1 }}, - { SDP2, { 2, 2 }}, - { SDP3, { 3, 3 }}, - { ONE_PPS, { -1, 5 }}, + /* name, gpio, delay */ + { SDP0, { 0, 0 }, { 0, 1 }}, + { SDP1, { 1, 1 }, { 0, 1 }}, + { SDP2, { 2, 2 }, { 0, 1 }}, + { SDP3, { 3, 3 }, { 0, 1 }}, + { ONE_PPS, { -1, 5 }, { 0, 1 }}, }; static const char ice_pin_names_nvm[][64] = { @@ -49,12 +49,12 @@ static const char ice_pin_names_nvm[][64] = { }; static const struct ice_ptp_pin_desc ice_pin_desc_e810_sma[] = { - /* name, gpio */ - { GNSS, { 1, -1 }}, - { SMA1, { 1, 0 }}, - { UFL1, { -1, 0 }}, - { SMA2, { 3, 2 }}, - { UFL2, { 3, -1 }}, + /* name, gpio, delay */ + { GNSS, { 1, -1 }, { 0, 0 }}, + { SMA1, { 1, 0 }, { 0, 1 }}, + { UFL1, { -1, 0 }, { 0, 1 }}, + { SMA2, { 3, 2 }, { 0, 1 }}, + { UFL2, { 3, -1 }, { 0, 0 }}, }; static struct ice_pf *ice_get_ctrl_pf(struct ice_pf *pf) @@ -1561,18 +1561,29 @@ void ice_ptp_extts_event(struct ice_pf *pf) * Event is defined in GLTSYN_EVNT_0 register */ for (chan = 0; chan < GLTSYN_EVNT_H_IDX_MAX; chan++) { + int pin_desc_idx; + /* Check if channel is enabled */ - if (pf->ptp.ext_ts_irq & (1 << chan)) { - lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx)); - hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx)); - event.timestamp = (((u64)hi) << 32) | lo; - event.type = PTP_CLOCK_EXTTS; - event.index = chan; - - /* Fire event */ - ptp_clock_event(pf->ptp.clock, &event); - pf->ptp.ext_ts_irq &= ~(1 << chan); + if (!(pf->ptp.ext_ts_irq & (1 << chan))) + continue; + + lo = rd32(hw, GLTSYN_EVNT_L(chan, tmr_idx)); + hi = rd32(hw, GLTSYN_EVNT_H(chan, tmr_idx)); + event.timestamp = (u64)hi << 32 | lo; + + /* Add delay compensation */ + pin_desc_idx = ice_ptp_find_pin_idx(pf, PTP_PF_EXTTS, chan); + if (pin_desc_idx >= 0) { + const struct ice_ptp_pin_desc *desc; + + desc = &pf->ptp.ice_pin_desc[pin_desc_idx]; + event.timestamp -= desc->delay[0]; } + + event.type = PTP_CLOCK_EXTTS; + event.index = chan; + pf->ptp.ext_ts_irq &= ~(1 << chan); + ptp_clock_event(pf->ptp.clock, &event); } } @@ -1767,6 +1778,7 @@ static int ice_ptp_write_perout(struct ice_hw *hw, unsigned int chan, static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq, int on) { + unsigned int gpio_pin, prop_delay; u64 clk, period, start, phase; struct ice_hw *hw = &pf->hw; unsigned int gpio_pin; @@ -1780,6 +1792,7 @@ static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq, return -EIO; gpio_pin = pf->ptp.ice_pin_desc[pin_desc_idx].gpio[1]; + prop_delay = pf->ptp.ice_pin_desc[pin_desc_idx].delay[1]; period = rq->period.sec * NSEC_PER_SEC + rq->period.nsec; /* If we're disabling the output or period is 0, clear out CLKO and TGT @@ -1811,11 +1824,11 @@ static int ice_ptp_cfg_perout(struct ice_pf *pf, struct ptp_perout_request *rq, * at the next multiple of period, maintaining phase. */ clk = ice_ptp_read_src_clk_reg(pf, NULL); - if (rq->flags & PTP_PEROUT_PHASE || start <= clk - ice_prop_delay(hw)) + if (rq->flags & PTP_PEROUT_PHASE || start <= clk - prop_delay) start = div64_u64(clk + period - 1, period) * period + phase; /* Compensate for propagation delay from the generator to the pin. */ - start -= ice_prop_delay(hw); + start -= prop_delay; return ice_ptp_write_perout(hw, rq->index, gpio_pin, start, period); } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.h b/drivers/net/ethernet/intel/ice/ice_ptp.h index 5af474285780..23cd7878bcc8 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp.h @@ -210,6 +210,7 @@ enum ice_ptp_pin_nvm { * struct ice_ptp_pin_desc - hardware pin description data * @name_idx: index of the name of pin in ice_pin_names * @gpio: the associated GPIO input and output pins + * @delay: input and output signal delays in nanoseconds * * Structure describing a PTP-capable GPIO pin that extends ptp_pin_desc array * for the device. Device families have separate sets of available pins with @@ -218,6 +219,7 @@ enum ice_ptp_pin_nvm { struct ice_ptp_pin_desc { int name_idx; int gpio[2]; + unsigned int delay[2]; }; /** diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h index 585ce200c60f..c3e9b78087a8 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_consts.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_consts.h @@ -341,8 +341,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 823437500, /* 823.4375 MHz PLL */ /* nominal_incval */ 0x136e44fabULL, - /* pps_delay */ - 11, }, /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */ @@ -351,8 +349,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 783360000, /* 783.36 MHz */ /* nominal_incval */ 0x146cc2177ULL, - /* pps_delay */ - 12, }, /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */ @@ -361,8 +357,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 796875000, /* 796.875 MHz */ /* nominal_incval */ 0x141414141ULL, - /* pps_delay */ - 12, }, /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */ @@ -371,8 +365,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 816000000, /* 816 MHz */ /* nominal_incval */ 0x139b9b9baULL, - /* pps_delay */ - 12, }, /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */ @@ -381,8 +373,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 830078125, /* 830.78125 MHz */ /* nominal_incval */ 0x134679aceULL, - /* pps_delay */ - 11, }, /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */ @@ -391,8 +381,6 @@ const struct ice_time_ref_info_e82x e82x_time_ref[NUM_ICE_TIME_REF_FREQ] = { 783360000, /* 783.36 MHz */ /* nominal_incval */ 0x146cc2177ULL, - /* pps_delay */ - 12, }, }; diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index f81e2e9b0200..790534a6a905 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -80,7 +80,6 @@ struct ice_phy_reg_info_eth56g { * struct ice_time_ref_info_e82x * @pll_freq: Frequency of PLL that drives timer ticks in Hz * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L - * @pps_delay: propagation delay of the PPS output signal * * Characteristic information for the various TIME_REF sources possible in the * E822 devices @@ -88,7 +87,6 @@ struct ice_phy_reg_info_eth56g { struct ice_time_ref_info_e82x { u64 pll_freq; u64 nominal_incval; - u8 pps_delay; }; /** @@ -326,9 +324,6 @@ extern const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD]; */ #define ICE_E810_PLL_FREQ 812500000 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL -#define ICE_E810_OUT_PROP_DELAY_NS 1 -#define ICE_E810_E830_SYNC_DELAY 0 -#define ICE_E825C_OUT_PROP_DELAY_NS 11 /* Device agnostic functions */ u8 ice_get_ptp_src_clock_index(struct ice_hw *hw); @@ -390,11 +385,6 @@ static inline u64 ice_e82x_nominal_incval(enum ice_time_ref_freq time_ref) return e82x_time_ref[time_ref].nominal_incval; } -static inline u64 ice_e82x_pps_delay(enum ice_time_ref_freq time_ref) -{ - return e82x_time_ref[time_ref].pps_delay; -} - /* E822 Vernier calibration functions */ int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port, bool soft_reset); int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port); @@ -431,20 +421,6 @@ int ice_phy_cfg_ptp_1step_eth56g(struct ice_hw *hw, u8 port); #define ICE_ETH56G_NOMINAL_THRESH4 0x7777 #define ICE_ETH56G_NOMINAL_TX_THRESH 0x6 -static inline u64 ice_prop_delay(const struct ice_hw *hw) -{ - switch (hw->mac_type) { - case ICE_MAC_E810: - return ICE_E810_OUT_PROP_DELAY_NS; - case ICE_MAC_GENERIC: - return ice_e82x_pps_delay(ice_e82x_time_ref(hw)); - case ICE_MAC_GENERIC_3K_E825: - return ICE_E825C_OUT_PROP_DELAY_NS; - default: - return 0; - } -} - /** * ice_get_base_incval - Get base clock increment value * @hw: pointer to the HW struct