diff mbox series

[v1,02/20] arm: socfpga: Add support for agilex5 clock manager

Message ID 20240920070242.20884-3-tien.fong.chee@intel.com
State New
Delegated to: TIEN FONG CHEE
Headers show
Series SoCFPGA: Add Boot Support for Agilex 5 in U-Boot | expand

Commit Message

Chee, Tien Fong Sept. 20, 2024, 7:02 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Adding mechanism to retrieve base address for Agilex5 Clock Mananger.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/mach-socfpga/misc.c | 24 ++++++++++++++----------
 1 file changed, 14 insertions(+), 10 deletions(-)

Comments

Marek Vasut Sept. 21, 2024, 1:47 p.m. UTC | #1 
On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Adding mechanism to retrieve base address for Agilex5 Clock Mananger.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Can this be turned into clock driver and probe from DT ?
Chee, Tien Fong Sept. 24, 2024, 5:58 a.m. UTC | #2 
Hi,

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Saturday, September 21, 2024 9:48 PM
> To: Chee, Tien Fong <tien.fong.chee@intel.com>; u-boot@lists.denx.de
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>; Meng, Tingting
> <tingting.meng@intel.com>; Yuslaimi, Alif Zakuan
> <alif.zakuan.yuslaimi@intel.com>; Hea, Kok Kiang
> <kok.kiang.hea@intel.com>
> Subject: Re: [PATCH v1 02/20] arm: socfpga: Add support for agilex5 clock
> manager
> 
> On 9/20/24 9:02 AM, tien.fong.chee@intel.com wrote:
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Adding mechanism to retrieve base address for Agilex5 Clock Mananger.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Can this be turned into clock driver and probe from DT ?

I will remove this patch, because I just noticed the clk driver for Agilex 5 is already in driver model (DT).

Regards,
Tien Fong.
diff mbox series

Patch

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 495ba2a0d41..6cf2ee60038 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -1,6 +1,6 @@ 
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2024 Altera Corporation <www.altera.com>
  */
 
 #include <config.h>
@@ -252,15 +252,19 @@  void socfpga_get_managers_addr(void)
 	if (ret)
 		hang();
 
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-	ret = socfpga_get_base_addr("intel,agilex-clkmgr",
-				    &socfpga_clkmgr_base);
-#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
-	ret = socfpga_get_base_addr("intel,n5x-clkmgr",
-				    &socfpga_clkmgr_base);
-#else
-	ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
-#endif
+	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
+		ret = socfpga_get_base_addr("intel,agilex-clkmgr",
+					    &socfpga_clkmgr_base);
+	else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+		ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+					    &socfpga_clkmgr_base);
+	else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+		ret = socfpga_get_base_addr("intel,agilex5-clkmgr",
+					    &socfpga_clkmgr_base);
+	else
+		ret = socfpga_get_base_addr("altr,clk-mgr",
+					    &socfpga_clkmgr_base);
+
 	if (ret)
 		hang();
 }