| Message ID | 20240829082830.56959-1-quic_varada@quicinc.com |
|---|---|
| Headers | show |
| Series | Add NSS clock controller support for Qualcomm IPQ5332 | expand |
On Thu, Aug 29, 2024 at 01:58:30PM GMT, Varadarajan Narayanan wrote: > From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > > NSSCC driver is needed to enable the ethernet interfaces and not > necessary for the bootup of the SoC, hence build it as a module. On which devices? > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 81ca46e3ab4b..2962bc079ddb 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -1307,6 +1307,7 @@ CONFIG_IPQ_GCC_5332=y > CONFIG_IPQ_GCC_6018=y > CONFIG_IPQ_GCC_8074=y > CONFIG_IPQ_GCC_9574=y > +CONFIG_IPQ_NSSCC_5332=m > CONFIG_MSM_GCC_8916=y > CONFIG_MSM_MMCC_8994=m > CONFIG_MSM_GCC_8994=y > -- > 2.34.1 >
On Thu, Aug 29, 2024 at 01:58:29PM GMT, Varadarajan Narayanan wrote: > From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > > Describe the NSS clock controller node and it's relevant external > clocks. Who generates these clocks? 300 MHz crystal? > > Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v5: Remove #power-domain-cells > Add #interconnect-cells > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 +++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 71328b223531..1cc614de845c 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -16,6 +16,18 @@ / { > #size-cells = <2>; > > clocks { > + cmn_pll_nss_200m_clk: cmn-pll-nss-200m-clk { > + compatible = "fixed-clock"; > + clock-frequency = <200000000>; > + #clock-cells = <0>; > + }; > + > + cmn_pll_nss_300m_clk: cmn-pll-nss-300m-clk { > + compatible = "fixed-clock"; > + clock-frequency = <300000000>; > + #clock-cells = <0>; > + }; > + > sleep_clk: sleep-clk { > compatible = "fixed-clock"; > #clock-cells = <0>; > @@ -479,6 +491,22 @@ frame@b128000 { > status = "disabled"; > }; > }; > + > + nsscc: clock-controller@39b00000 { > + compatible = "qcom,ipq5332-nsscc"; > + reg = <0x39b00000 0x80000>; > + clocks = <&cmn_pll_nss_200m_clk>, > + <&cmn_pll_nss_300m_clk>, > + <&gcc GPLL0_OUT_AUX>, > + <0>, > + <0>, > + <0>, > + <0>, > + <&xo_board>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #interconnect-cells = <1>; > + }; > }; > > timer { > -- > 2.34.1 >
On Thu, Aug 29, 2024 at 01:58:27PM GMT, Varadarajan Narayanan wrote: > Update the GCC master/slave list to include couple of > more interfaces needed by the Network Subsystem Clock > Controller (NSSCC) > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > drivers/clk/qcom/gcc-ipq5332.c | 2 ++ > 1 file changed, 2 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Add bindings, driver and devicetree node for networking sub system clock controller on IPQ5332. Some of the nssnoc clocks present in GCC driver is enabled by default and its RCG is configured by bootloaders, so enable those clocks in driver probe. Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> --- Changes in v5: - Rebased on next-20240821 - Addressed review comments - Dropped 'const qualifier' patches - Dropped 'clk: qcom: ipq5332: enable few nssnoc clocks in driver probe' - Enabled icc-clk for NSSCC - Update ICC master/slave list - In dt-bindings of nsscc Mark #power-domain-cells as false (as it is not applicable) Add #interconnect-cells - Link to v4: https://lore.kernel.org/lkml/20240122-ipq5332-nsscc-v4-0-19fa30019770@quicinc.com/ Changes in v4: - Rebased on next-20240122 - Fixed the missing space on the nsscc node - Link to v3: https://lore.kernel.org/linux-arm-msm/20231211-ipq5332-nsscc-v3-0-ad13bef9b137@quicinc.com/ Changes in v3: - Collected the tags - Dropped the dt-binding patch 3/9 - Cleaned up the header file inclusion and updated the module description in the driver - Used the decimal number instead of hex in the NSSCC node - Link to v2: https://lore.kernel.org/r/20231121-ipq5332-nsscc-v2-0-a7ff61beab72@quicinc.com Changes in v2: - Change logs are in respective patches - Link to v1: https://lore.kernel.org/r/20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com --- Kathiravan Thirumoorthy (6): dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock clk: qcom: ipq5332: add gpll0_out_aux clock dt-bindings: clock: add Qualcomm IPQ5332 NSSCC clock and reset definitions clk: qcom: add NSS clock Controller driver for Qualcomm IPQ5332 arm64: dts: qcom: ipq5332: add support for the NSSCC arm64: defconfig: build NSS Clock Controller driver for Qualcomm IPQ5332 Varadarajan Narayanan (2): dt-bindings: interconnect: Update master/slave id list clk: qcom: ipq5332: Add couple of more interconnects .../bindings/clock/qcom,ipq5332-nsscc.yaml | 64 + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 + arch/arm64/configs/defconfig | 1 + drivers/clk/qcom/Kconfig | 9 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq5332.c | 16 + drivers/clk/qcom/nsscc-ipq5332.c | 1049 +++++++++++++++++ include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + .../dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++ .../dt-bindings/interconnect/qcom,ipq5332.h | 4 + 10 files changed, 1259 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml create mode 100644 drivers/clk/qcom/nsscc-ipq5332.c create mode 100644 include/dt-bindings/clock/qcom,ipq5332-nsscc.h