| Message ID | 20240828023342.1676130-1-haochen.jiang@intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [gcc-wwwdocs] gcc-15: Mention recent update for x86_64 backend | expand |
On Wed, 28 Aug 2024, Haochen Jiang wrote: > Sorry for the disturb since I mis-typoed gcc-patches to gcc-patchs, > resend the patch. No worries. > This patch will add documentation for recent update in x86-64 backend. Thank you! > + <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) were removed I believe "Support for Xeon Phi CPUs" or "Xeon Phi CPU support" would be better, though not 100% sure. > + in GCC 15. GCC will no longer accept <code>-mavx5124fmaps</code>, > + <code>-mavx5124vnniw</code>, <code>-mavx512er</code>, > + <code>-mavx512pf</code>, <code>-mprefetchwt1</code>, > + <code>-march=knl</code>, <code>-march=knm</code>, <code>-mtune=knl</code> > + or <code>-mtune=knm</code> compiler switches. Is there a particular rationale for the order of switches? If not, I'd sort them alphabetically (which is partially the case already) and start with -march=... The patch is okay if you consider (which is not necessarily making) these changes. Gerald
> -----Original Message----- > From: Gerald Pfeifer <gerald@pfeifer.com> > Sent: Thursday, August 29, 2024 3:20 AM > > On Wed, 28 Aug 2024, Haochen Jiang wrote: > > Sorry for the disturb since I mis-typoed gcc-patches to gcc-patchs, > > resend the patch. > > No worries. > > > This patch will add documentation for recent update in x86-64 backend. > > Thank you! > > > + <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) > > + were removed > > I believe "Support for Xeon Phi CPUs" or "Xeon Phi CPU support" would be better, > though not 100% sure. > > > + in GCC 15. GCC will no longer accept <code>-mavx5124fmaps</code>, > > + <code>-mavx5124vnniw</code>, <code>-mavx512er</code>, > > + <code>-mavx512pf</code>, <code>-mprefetchwt1</code>, > > + <code>-march=knl</code>, <code>-march=knm</code>, <code>- > mtune=knl</code> > > + or <code>-mtune=knm</code> compiler switches. > > Is there a particular rationale for the order of switches? If not, I'd sort them > alphabetically (which is partially the case already) and start with -march=... > > The patch is okay if you consider (which is not necessarily making) these changes. I will change them and commit them tomorrow if there is no objection. Thx, Haochen > > Gerald
diff --git a/htdocs/gcc-15/changes.html b/htdocs/gcc-15/changes.html index d0d6d147..4cb0fa90 100644 --- a/htdocs/gcc-15/changes.html +++ b/htdocs/gcc-15/changes.html @@ -132,7 +132,23 @@ a work-in-progress.</p> code like <code>1 << offset</code> is not fast enough.</li> </ul> -<!-- <h3 id="x86">IA-32/x86-64</h3> --> +<h3 id="x86">IA-32/x86-64</h3> + +<ul> + <li>New ISA extension support for Intel AVX10.2 was added. + AVX10.2 intrinsics are available via the <code>-mavx10.2</code> or + <code>-mavx10.2-256</code> compiler switch with 256-bit vector size + support. 512-bit vector size support for AVX10.2 intrinsics are + available via the <code>-mavx10.2-512</code> compiler switch. + </li> + <li>Xeon Phi CPUs support (a.k.a. Knight Landing and Knight Mill) were removed + in GCC 15. GCC will no longer accept <code>-mavx5124fmaps</code>, + <code>-mavx5124vnniw</code>, <code>-mavx512er</code>, + <code>-mavx512pf</code>, <code>-mprefetchwt1</code>, + <code>-march=knl</code>, <code>-march=knm</code>, <code>-mtune=knl</code> + or <code>-mtune=knm</code> compiler switches. + </li> +</ul> <!-- <h3 id="mips">MIPS</h3> -->