| Message ID | 20240824220701.97796-1-naoki@radxa.com |
|---|---|
| State | Superseded |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | rockchip: add SPI NOR flash support for Radxa E25(CM3I) | expand |
sorry, please ignore this patch. https://patchwork.ozlabs.org/project/uboot/patch/20240824220847.98136-1-naoki@radxa.com/ is right one. -- FUKAUMI Naoki Radxa Computer (Shenzhen) Co., Ltd. On 8/25/24 07:07, FUKAUMI Naoki wrote: > some SKU for CM3I SoM have a SPI NOR flash. this patch enables related > configurations and changes devicetree. > > => sf probe > SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB > > Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> > --- > Changes in v2: > - reword commit message > --- > arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 ++++++++++++++++ > configs/radxa-e25-rk3568_defconfig | 14 ++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi > index 74755a44eae..1f0bacbf61f 100644 > --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi > +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi > @@ -21,6 +21,22 @@ > mmc-hs400-enhanced-strobe; > }; > > +&sfc { > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + bootph-pre-ram; > + bootph-some-ram; > + spi-max-frequency = <24000000>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <1>; > + }; > +}; > + > &usb_host0_xhci { > dr_mode = "host"; > }; > diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig > index 496fee0e0a4..51bf0287198 100644 > --- a/configs/radxa-e25-rk3568_defconfig > +++ b/configs/radxa-e25-rk3568_defconfig > @@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y > CONFIG_SYS_HAS_NONCACHED_MEMORY=y > CONFIG_COUNTER_FREQUENCY=24000000 > CONFIG_ARCH_ROCKCHIP=y > +CONFIG_SF_DEFAULT_SPEED=24000000 > +CONFIG_SF_DEFAULT_MODE=0x2000 > CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25" > CONFIG_ROCKCHIP_RK3568=y > +CONFIG_ROCKCHIP_SPI_IMAGE=y > CONFIG_SPL_SERIAL=y > CONFIG_DEBUG_UART_BASE=0xFE660000 > CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_SPL_SPI_FLASH_SUPPORT=y > +CONFIG_SPL_SPI=y > CONFIG_SYS_LOAD_ADDR=0xc00800 > CONFIG_PCI=y > CONFIG_DEBUG_UART=y > @@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_SPL_MAX_SIZE=0x40000 > CONFIG_SPL_PAD_TO=0x7f8000 > # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set > +CONFIG_SPL_SPI_LOAD=y > +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 > CONFIG_SPL_ATF=y > CONFIG_CMD_GPIO=y > CONFIG_CMD_GPT=y > @@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SDHCI=y > CONFIG_MMC_SDHCI_SDMA=y > CONFIG_MMC_SDHCI_ROCKCHIP=y > +CONFIG_SF_DEFAULT_BUS=4 > +CONFIG_SPI_FLASH_SFDP_SUPPORT=y > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_WINBOND=y > +CONFIG_SPI_FLASH_XTX=y > CONFIG_RTL8169=y > CONFIG_PCIE_DW_ROCKCHIP=y > CONFIG_PHY_ROCKCHIP_INNO_USB2=y > @@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y > CONFIG_SCSI=y > CONFIG_DEBUG_UART_SHIFT=2 > CONFIG_SYS_NS16550_MEM32=y > +CONFIG_ROCKCHIP_SFC=y > CONFIG_SYSRESET=y > CONFIG_USB=y > CONFIG_USB_XHCI_HCD=y
Hi Naoki, On 8/25/24 12:07 AM, FUKAUMI Naoki wrote: > some SKU for CM3I SoM have a SPI NOR flash. this patch enables related > configurations and changes devicetree. > > => sf probe > SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB > > Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> > --- > Changes in v2: > - reword commit message > --- > arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 ++++++++++++++++ > configs/radxa-e25-rk3568_defconfig | 14 ++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi > index 74755a44eae..1f0bacbf61f 100644 > --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi > +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi > @@ -21,6 +21,22 @@ > mmc-hs400-enhanced-strobe; > }; > > +&sfc { > + #address-cells = <1>; > + #size-cells = <0>; > + status = "okay"; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + bootph-pre-ram; > + bootph-some-ram; > + spi-max-frequency = <24000000>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <1>; > + }; > +}; > + Was this sent upstream to the Linux kernel already? I did a very quick search on lore.kernel.org and didn't find anything. Is there anything that's preventing you from sending this to them first? I really would prefer to have only U-Boot specific stuff in -u-boot.dtsi DTSIs. Cheers, Quentin
hi, On 8/27/24 01:11, Quentin Schulz wrote: > Hi Naoki, > > On 8/25/24 12:07 AM, FUKAUMI Naoki wrote: >> some SKU for CM3I SoM have a SPI NOR flash. this patch enables related >> configurations and changes devicetree. >> >> => sf probe >> SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, >> total 16 MiB >> >> Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> >> --- >> Changes in v2: >> - reword commit message >> --- >> arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 ++++++++++++++++ >> configs/radxa-e25-rk3568_defconfig | 14 ++++++++++++++ >> 2 files changed, 30 insertions(+) >> >> diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi >> b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi >> index 74755a44eae..1f0bacbf61f 100644 >> --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi >> +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi >> @@ -21,6 +21,22 @@ >> mmc-hs400-enhanced-strobe; >> }; >> +&sfc { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + status = "okay"; >> + >> + flash@0 { >> + compatible = "jedec,spi-nor"; >> + reg = <0>; >> + bootph-pre-ram; >> + bootph-some-ram; >> + spi-max-frequency = <24000000>; >> + spi-rx-bus-width = <4>; >> + spi-tx-bus-width = <1>; >> + }; >> +}; >> + > > Was this sent upstream to the Linux kernel already? I did a very quick > search on lore.kernel.org and didn't find anything. Is there anything > that's preventing you from sending this to them first? I really would > prefer to have only U-Boot specific stuff in -u-boot.dtsi DTSIs. no, not yet, but I'll send this to Linux ASAP. since SPI NOR flash is used for U-Boot, I sent this to here first. Best regards, -- FUKAUMI Naoki Radxa Computer (Shenzhen) Co., Ltd. > Cheers, > Quentin >
diff --git a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi index 74755a44eae..1f0bacbf61f 100644 --- a/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi +++ b/arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi @@ -21,6 +21,22 @@ mmc-hs400-enhanced-strobe; }; +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + bootph-pre-ram; + bootph-some-ram; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + &usb_host0_xhci { dr_mode = "host"; }; diff --git a/configs/radxa-e25-rk3568_defconfig b/configs/radxa-e25-rk3568_defconfig index 496fee0e0a4..51bf0287198 100644 --- a/configs/radxa-e25-rk3568_defconfig +++ b/configs/radxa-e25-rk3568_defconfig @@ -3,11 +3,16 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y +CONFIG_SF_DEFAULT_SPEED=24000000 +CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-radxa-e25" CONFIG_ROCKCHIP_RK3568=y +CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y CONFIG_DEBUG_UART_BASE=0xFE660000 CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_PCI=y CONFIG_DEBUG_UART=y @@ -23,6 +28,8 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x40000 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 CONFIG_SPL_ATF=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y @@ -51,6 +58,12 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SF_DEFAULT_BUS=4 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XTX=y CONFIG_RTL8169=y CONFIG_PCIE_DW_ROCKCHIP=y CONFIG_PHY_ROCKCHIP_INNO_USB2=y @@ -64,6 +77,7 @@ CONFIG_SPL_RAM=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y
some SKU for CM3I SoM have a SPI NOR flash. this patch enables related configurations and changes devicetree. => sf probe SF: Detected w25q128fw with page size 256 Bytes, erase size 4 KiB, total 16 MiB Signed-off-by: FUKAUMI Naoki <naoki@radxa.com> --- Changes in v2: - reword commit message --- arch/arm/dts/rk3568-radxa-e25-u-boot.dtsi | 16 ++++++++++++++++ configs/radxa-e25-rk3568_defconfig | 14 ++++++++++++++ 2 files changed, 30 insertions(+)